NoC

Introduction

NoC: Network-on-Chip is a new on-chip communication architecture designed for multi-core SoCs. For the delay, communication performance bottlenecks and design efficiency problems in the traditional shared bus communication structure, NoC provides a new on-chip communication structure solution. This article first discusses the current research status of NoC at home and abroad, and then discusses the system chip design process using NoC as the communication architecture. On this basis, we analyzed the performance characteristics, routing algorithms, and single router node power consumption and performance evaluation models of NoC in the two-dimensional network NoC topology, and simultaneously performed the performance and hardware overhead of the common on-chip shared bus Comparison. At the same time, low power consumption is a trend in the design of very large scale integrated circuits, especially for some embedded systems, mobile terminals and handheld devices. For NoC design, the energy consumption of NoC can be reduced at various levels, such as physical layer, link layer, network layer, application layer, etc. This article focuses on the NoC on-chip communication architecture, mainly studies the technology and performance analysis methods for low-power design at the network layer and application layer. Its main work is as follows: First, for ultra-deep submicron semiconductor technology, the data on-chip communication is complete The problem of increasing seriousness has proposed an adaptive NoC link data protection method. According to the error probability of the communication link and the reliability constraint requirements of the system, this method adaptively compromises the reliability level and power consumption of the on-chip communication link, so that while meeting the data integrity requirements of the on-chip communication link, NoC Of communication energy consumption is minimal. Secondly, according to the characteristics of NoC adopting network communication, a delay calculation method of NoC message based on network integration is proposed. This method calculates the transmission delay of the message in the NoC by analyzing the arrival curve of the input message and the service curve of the routing node, and uses the network integration theory; at the same time, it uses the message delay calculation method of different arbitration strategies for the routing node in the NoC The research was conducted and compared with the cycle accuracy simulation in accuracy. Again, for the two key steps of IP core mapping and route allocation in the NoC design process, a low-power IP core mapping and link balancing routing customization algorithm PLBMR based on PSO is proposed. For the two-dimensional grid NoC, based on the mathematical calculation method of NoC energy consumption and communication link load balancing, the PSO particle representation problem of IP core mapping and routing allocation is solved. However, for different applications, the type of communication data flow between IPs will be very different. In order to obtain optimized performance, it is necessary to set appropriate algorithm parameters according to specific applications. Finally, for the irregular 2D NoC topology, a low-power fully customized routing algorithm EA_TP to avoid deadlock is proposed. The routing algorithm is based on the deadlock avoidance routing algorithm of turn prohibition, considering the two factors of link length and communication capacity on the link, selecting the appropriate turn is prohibited, while ensuring full connection of NoC, and then using Dijkstra's shortest path routing algorithm , To construct routing paths for all communication flows. The EA_TP algorithm uses the routing table method to construct customized routes, which ensures that within a reasonable area cost range, it solves the problem of irregular NoC deadlocks and at the same time minimizes the NoC communication energy consumption.