BRAM

Introduction

Block RAM (BRAM): Block random access memory.

Xlinx's SP3 series FPGAs include two types of RAM: Block RAM and Distributed RAM.

SP3 contains Block RAM of up to 1.87Mbit, which is mainly used to construct data cache, deep FIFO and buffer.

Each Block RAM is 18Kbit, the structure is a true dual-port RAM, including two complete sets of 36bit read and write data bus and corresponding control bus. Each Block RAM can be configured as a single-port RAM (maximum bandwidth is 72bit) or dual-port RAM (maximum bandwidth is 36bit), and supports cascading, which can cascade up to 104 synchronized 18Kbit Block RAM. SP3's Block RAM supports multiple aspect ratios, multiple data bandwidth conversions, and supports parity operations.

Difference with Distributed Ram

The lock ram must be used up all at once. If the resource you instantiate is less than a block ram, but the block ram is also occupied and cannot be used elsewhere. Distributed RAM does not waste as much as it uses and occupies.