Slice

Introduction

SLICE constitutes the basic unit CLB (Configurable Logic Block) in FPGA. The composition of SLICE in different FPGA chips is slightly different, for example:

A CLB of Xilinx Virtex-5 FPGA contains two slices. Each slice contains 4 LUTs (lookup tables), 4 flip-flops, multiplexers and carry chains. Some slices also include distributed RAM and 32-bit shift registers. This slice is called SLICEM, and other slices are called SLICEL. The two slices in the CLB are independent of each other, and each is connected to a switch matrix (Switch Matrix) to connect with a general routing matrix (General routing Matrix).

In the Xilinx FPGA design tool, the position of the slice is represented by "XmYn", where m is the horizontal coordinate of the slice, the horizontal coordinates of two slices of a CLB are m and m+1; n is the vertical coordinate of the CLB, and a CLB Of the two slices have the same n. The slice number in the lower left corner of Virtex-5 is X0Y0.

In fact, the lookup table is similar to a ROM, the capacity is 64bit, 6 inputs are used as address input, and the stored content is used as the result of Boolean operation. The content in the lookup table is generated by ISE and loaded into it during FPGA configuration.

The flip-flop in Slice can be configured into multiple working modes, such as FF or Latch, synchronous reset or asynchronous reset, reset high or low effective, etc.

Slice

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