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CLB (Configurable Logic Block) is a product composed of input and output modules and programmable interconnection bus.  Configurable logic block is the basic logic unit in FPGA. Each CLB contains a configurable switch matrix. This matrix consists of 4 or 6 inputs and some selection circuits (multiplexer) Etc.) and triggers. In Xilinx's FPGA devices, CLB consists of multiple (generally 4 or 2) identical slices and additional logic.


Configurable logic module

CLB (Configurable Logic Block)

The unit FPGA mainly consists of three parts:

Configurable logic block CLB (Configurable Logic Block)

Input/output module I/OB and programmable interconnect bus PI (Programmable Interconnect)

For chips of different specifications, they can contain 8×8, 20×20, 44×44 or even 92×92 CLB arrays, and are equipped with 64, 160, 352, or even 448 I/OB and programmable wiring for realizing Necessary other components.

The CLB contains a configurable switch matrix. This matrix consists of a selection circuit (multiplexer), flip-flop and 4 or 6 inputs. In FPGA devices of Xilinx, CLB consists of multiple (generally 4 or 2) identical slices and additional logic. Each CLB module can not only be used to implement combinational logic and sequential logic, but also can be configured as distributed RAM and distributed ROM.

The Spartan-3E family architecture consists of five fundamental programmable functional elements:

· Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.

· Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included.

· Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

· Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.

· Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

The architecture of Xilinx's Spartan-3E series products consists of five elements with basic programmable functions:

1. Configurable logic function CLB block contains a flexible lookup table structure that can implement logic plus storage elements such as flip-flops and latches, perform various logic functions and store data

2. The input and output block IOB controls the data flow between I/O pins and internal logic devices. Each IOB supports bidirectional data flow and tri-state operation, and supports multiple signal standards-including four high-performance differential standards

3. The memory block supports a dual-port block with a data storage form of 18000 bits

4. The multiplier block accepts two 18-bit binary numbers as input and temporarily stores the calculation result

5. Data clock manager DCM provides self-calibration, all-digital solution for clock signal distribution, delay, frequency multiplication, frequency division, and phase shift.

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