RISC-V (pronounced "risk-five") is an open source instruction set architecture (ISA) based on the principles of reduced instruction set (RISC).
RISC-V (pronounced "RISC-FIVE") is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). V is the fifth generation RISC (reduced instruction set computer), which means that it has been four RISC processor prototype chip. Each generation of RISC processors is completed under the leadership of the same person, and that is Professor David A. Patterson of the University of California, Berkeley. Contrary to most ISAs, RISC-V ISA can be used free of charge in all desired equipment, allowing anyone to design, manufacture and sell RISC-V chips and software. Figure 1 shows the prototype chip of the previous four-generation RISC processor. Although it is not the first open source instruction set (ISA), it is important because it is the first instruction set architecture that can be selected according to specific scenarios. Based on the RISC-V instruction set architecture, server CPUs, home appliance CPUs, industrial control CPUs, and CPUs used in sensors smaller than fingers can be designed.
The RISC-V Foundation does not charge high authorization fees for the use of instruction sets. Open source adopts the loose BSD protocol, and the enterprise is completely free to use it. It also allows enterprises to add their own instruction set expansion without having to open and share to achieve differentiated development.
The RISC-V architecture adheres to a simple design philosophy. Reflected:
In the processor field, the mainstream architecture is x86 and ARM architecture. The development process of x86 and ARM architecture is also accompanied by the continuous development and maturity of modern processor architecture technology, but as a commercial architecture, in order to maintain the backward compatibility of the architecture, it has to retain many outdated definitions, resulting in the number of instructions Many, instruction redundancy is serious, and the number of documents is huge, so it is very high to develop a new operating system on these architectures or directly develop applications. The RISC-V architecture can completely abandon the burden, with the help of computer architecture after years of development has become the advantage of a more mature technology, starting from the light. The basic instruction set of RISC-V is only more than 40, plus dozens of instructions with other modular expansion instructions. The RISC-V specification document is only 145 pages, while the "privileged architecture document" is only 91 pages.
Modern operating systems have done the separation of privilege-level instructions and user-level instructions. Privileged instructions can only be called by the operating system, while user-level instructions can only be called in user mode to ensure the stability of the operating system. RISC-V provides privileged instructions and user-level instructions, and provides detailed information of the RISC-V privileged instruction specifications and RISC-V user-level instruction specifications, allowing developers to easily port linux and unix systems to RISC-V platform.
The RISC-V architecture is not only short and sophisticated, but its different parts can also be organized together in a modular manner, thus trying to meet a variety of different application scenarios through a unified architecture. Users can flexibly choose different combinations of modules to meet their needs for customized equipment. For example, for small-area low-power embedded scenarios, users can select the instruction set of the RV32IC combination and only use Machine Mode; and high For performance application operating system scenarios, you can select, for example, the instruction set of RV32IMFDC, using Machine Mode and User Mode.
For designing a CPU, the tool chain is a window for software developers to interact with the CPU. Without a tool chain, the software developer has high requirements for developing software, and even the software developer cannot make the CPU work. In CPU design, the development of tool chain is a job that requires a huge amount of work. If RISC-V is used to design chips, chip design companies no longer have to worry about tool chain issues, just focus on chip design. The RISC-V community has provided a complete tool chain, and the RISC-V Foundation continues to maintain the tool chain. The current RISC-V support has been merged into the main tools, such as compilation tool chain gcc, simulation tool qemu, etc.
BOOM: Christopher Celio's RV64 out-of-order processor implementation. Chisel, BSD Licensed.
BottleRocket: RV32IMC microprocessor. Chisel, Apache Licensed.
bwitherspoon: RV32 microprocessor. SystemVerilog, ISC Licensed.
Clarvi: RISC-V processor for teaching at Cambridge University. SystemVerilog, BSD Licensed.
F32: RV32 microprocessor for FPGA, VHDL, BSD Licensed.
GRVI: Gray Research LLC. RV32 microprocessor optimized for FPGA, commercial licensed.
Hummingbird E200. Two-stage pipeline, the target is to replace Cortex-M0/8051, Verilog, Apache 2.0 licensed.
invicta: RV32 microprocessor of the first-stage pipeline. Verilog, BSD Licensed.
Kamikaze: RV32 microprocessor. Verilog, MIT Liencensed.
KCP53000: RV64 processor implementation of Samuel A. Falvo II. Verilog, MPL Licensed.
nanorv32: 2 machine pipeline RV32 implementation. Verilog, GPLv2 Licensed.
OpenV: Open source microprocessor supporting RV32, Verilog, MIT Licensed, OnChipUIS, from Universidad Industrial de Santander in Colombia.
ORCA: Open source microprocessor supporting RV32, VHDL, BSD Licensed, VectorBlox.
PicoRV32: Clifford Wolf designed (for FPGA) RV32 microprocessor, Verilog, ISC Licensed.
Potato: RV32 microprocessor for FPGA. VHDL, BSD Licensed.
RI5CY: Open source microprocessor supporting RV32
PULPino: SystemVerilog, Solderpad Licensed, PULP project from Zurich University of Technology and University of Bologna.
River: GNSS Senor Ltd. RV64 processor based on Rocket architecture. VHDL, BSD Licensed.
Rocket: Open source processor supporting RV64/32
Rocket-Chip: Chisel, BSD Licensed, Free chips project, open source project separated by UC Berkeley.
Freedom: Chisel, a start-up separated from Apache Licensed, SiFive, UC Berkeley.
lowRISC: Chisel+SystemVerilog, Solderpad Licensed, a non-profit organization initiated from Cambridge University.
RoCC: the Rocket customized coprocessor interface A co-processor interface that is closely interconnected with Rocket processors.
RV12: RoaLogic's RV32 microprocessor. Verilog, RoaLogic non-commercial Licensed.
SCR1: Syntacore's RV32 open source microprocessor. SystemVerilog, Solerpad Licensed.
SHAKTI: Indian IIT-Madras RISC-V processor series, Bluespec, BSD Licensed.
Sodor: RISC-V processor for teaching. Chisel, BSD Licensed.
uRV: RV32 microprocessor for FPGA. Verilog, LGPLv3 Licensed.
VexRiscv: RV32 microprocessor for FPGA written in SpinalHDL. SpinalHDL, MIT Licensed.
YARVI: RV32I microprocessor designed by Tommy Thorn, Verilog, GPL2v Licensed.
There have been cases of streaming by institutions and commercial companies. Follow the RISC-V community for specific information.
Complete tool chain maintenance, a large number of open source projects. The risc-v google discussion group (name: RISC-V ISA Dev) attracted volunteers from all over the world to participate in the discussion to continuously improve the risc-v architecture.
FPGA XC4000E Family 25K Gates 2432 Cells 0.35um Technology 5V 304-Pin HSPQFP EP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 320-Pin FBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 320-Pin FBGA