In 2004, Altera officially launched the Nios II series of 32-bit RISC embedded processors. The Nios II series of soft-core processors are Altera's second-generation FPGA embedded processors. Their performance exceeds 200 DMIPS and can be implemented in Altera FPGAs at only 35 cents. Altera's Stratix, Stratix GX, Stratix II and Cyclone series FPGAs fully support Nios II processors, and future FPGA devices will also support Nios II.
Since the launch of the first-generation 16-bit Nios processor in 2000, more than 13,000 Nios development kits have been delivered, and Nios has become the most popular soft-core processor. The Nios Ⅱ series, launched in June 2004, uses a brand new architecture and has a higher level of efficiency and performance than the first-generation Nios. Compared with the first generation, the Nios II core takes up less than 50% of FPGA resources on average, while the computing performance has doubled.
Nios Ⅱ series
Includes 3 products, namely: Nios Ⅱ/f (fast)-the highest system performance, medium FPGA usage; Nios Ⅱ/s (standard)-high performance, low FPGA usage; Nios Ⅱ/e (economic )-Low performance and lowest FPGA usage. These three products have the basic structural unit of a 32-bit processor-32-bit instruction size, 32-bit data and address path, 32-bit general-purpose registers and 32 external interrupt sources; using the same instruction set architecture (ISA), 100% Binary code is compatible. Designers can change the CPU according to changes in system requirements and choose the best solution that meets performance and cost without affecting existing software investment.
In particular, the Nios II series supports the use of special instructions. The dedicated instruction is a hardware module added by the user, which adds an arithmetic logic unit (ALU). Users can create up to 256 dedicated instructions for each Nios II processor used in the system, which allows designers to fine-tune the system hardware to meet performance goals. The dedicated instruction logic is the same as the Nios II instruction itself, and can take values from up to two source registers, and optionally write the results back to the target register. At the same time, Nios Ⅱ series supports more than 60 peripheral options, developers can choose the appropriate peripherals, get the most suitable combination of processor, peripherals and interfaces, without having to pay for the silicon function that is not used at all.
It can meet the needs of any application 32-bit embedded microprocessor. Customers can transplant the first-generation Nios processor design to a certain Nios II processor. Altera will support the first-generation Nios processor on the existing FPGA series for a long time. In addition, Altera provides a one-click migration option that can be upgraded to the Nios II series. Nios Ⅱ processors can also be implemented in HardCopy devices. Altera also provides ASIC porting for systems based on Nios Ⅱ processors.
Nios Ⅱ processor has a complete software development kit, including compiler, integrated development environment (IDE), JTAG debugger, real-time operating system (RTOS) and TCP/IP protocol stack. Designers can use the SOPC Builder system development tool in the Altera Quartus Ⅱ development software to easily create a dedicated processor system, and can add the number of Nios Ⅱ processor cores according to system requirements.
The Nios Ⅱ software development tool can be used to build software for the Nios Ⅱ system, that is, one-click automatic generation of a dedicated C/C++ operating environment suitable for system hardware. Nios Ⅱ Integrated Development Environment (IDE) provides many software templates to simplify project settings. In addition, the Nios II development kit includes two third-party real-time operating systems (RTOS)-MicroC/OS-II (Micrium), Nucleus Plus (ATI/Mentor), and a TCP/IP protocol stack for network applications.
The reason why Altera has been pursuing an embedded processor strategy for a long time is that as the development of applied ASICs is increasingly troubled by costs, OEMs are increasingly turning to FPGAs to build their own systems. The vast majority of these systems require a processor, and Altera provides designers with flexible embedded processor solutions optimized for FPGAs that can meet the needs of the 16-bit and 32-bit embedded processor markets. It is estimated that by 2007, the market value will reach 11 billion US dollars.
The advantage of using a soft-core processor in an FPGA over a hard-core is that the hard-core implementation has no flexibility and often cannot use the latest technology. As the system becomes more advanced, the solution based on the standard processor will be eliminated, and the solution based on the Nios Ⅱ processor is built on the HDL source code, which can be modified to meet the new system requirements and avoid the fate of being eliminated. By implementing the processor as an IP core of HDL, developers can fully customize the CPU and peripherals to obtain a processor that just meets the needs.
The Nios Ⅱ series of embedded processors are optimized for Altera FPGA and programmable system-on-chip (SOPC) integration applications. Table 1 details the characteristics of the Nios II soft core embedded processor series. For more general information, please refer to the Nios II introduction page.
Design process and tools
Hardware Development Tools This page details the development tools used to build the Nios Ⅱ processor hardware system.
Software development tools This page provides information about the Nios Ⅱ integrated development environment (IDE), which is a widely used developer's integrated development environment that includes functions such as editing, compiling, and debugging application software.
Development Kit Altera and its partners provide a large number of development board kits that use the Nios II series of embedded processors.
System-level design flow Altera's SOPC Builder tool provides the ability to quickly build SOPC systems. This architecture can be a complex system that contains one or several CPUs, provides memory interfaces, peripheral devices, and system interconnect logic.
Nios Ⅱ processor core The Nios Ⅱ processor series consists of three different cores, which can flexibly control cost and performance, and thus has a wide range of application space.
JTAG debugging module The JTAG debugging module provides on-chip control, debugging and communication functions of the Nios II processor through a remote PC host. This is a very competitive feature of the Nios II processor.
User instructions Developers can add hardware to the Nios Ⅱ CPU core to perform complex computing tasks and provide accelerated algorithms for software with tight timing requirements.
Peripheral equipment and interface Nios Ⅱ development kit includes a set of standard peripheral equipment library, which can be used for free in Altera FPGA.
Avalon™ switched bus Avalon switched bus implements network connections between processors, peripherals, and interface circuits, and provides high-bandwidth data paths, multiplexing, and real-time processing capabilities. Avalon switched bus can be automatically generated by calling SOPC Builder design software.
Nios Ⅱ processor support The Nios Ⅱ processor support page provides a variety of information helpful to Nios Ⅱ designers, including licenses, downloads, reference designs, documentation, online displays, and frequently asked questions.
Embedded Processor Solution Center The Embedded Processor Solution Center provides a lot of information to help developers use Altera's embedded processors to implement system design. The available information includes device support, software development tools, peripheral equipment and interfaces, training, technical support, and documentation.
Nios renewal information The Nios II development kit includes a one-year upgrade license for CPU, peripherals, and embedded software development tools. (This does not include Quartus II software upgrades.) Customers can order additional information including Nios II processor upgrades every year through the Nios renewal program.
Nios Ⅱ Embedded Processor Q&A page This page provides common questions and answers for Altera Nios Ⅱ series embedded processors.
Stratix Ⅱ device and Nios Ⅱ processor series The excellent characteristics of Stratix Ⅱ device structure and Nios Ⅱ embedded processor series combine to provide unparalleled processing power, satisfying network, communication, data signal processing (DSP) applications, mass storage and Application requirements of other high-bandwidth systems.
The excellent characteristics of the Stratix FPGA structure combined with the Nios Ⅱ embedded processor provides a high processing capacity to meet the needs of high-bandwidth system applications.
Cyclone™ devices and Nios Ⅱ processor series The Nios Ⅱ embedded processor series is used in Cyclone devices to reduce costs and increase flexibility. It provides an ideal alternative to low-cost discrete microprocessors in price-sensitive applications Goods.
Core device: Nios Ⅱ
.clock (s1_clk), file://s1_clk is the clock signal from the S1 port on the Avalon bus module
.aclr (s1_reset), file://s1_reset is the reset signal from the S1 port on the Avalon bus module
.q (s1_readdata), file://s1_readdata is the 32-bit data flowing to the S1 port of the Avalon bus module
.address (s1_address) file://s1_address is the address from the S1 port of the Avalon bus module
file://Control register read/write port (S2):
control_register the control_register
.clk (s2_clk), file://s2_clk is the clock signal from the S2 port on the Avalon bus module
.reset (s2_reset), file://s2_reset is the reset signal from the S2 port on the Avalon bus module
.read (s2_read), file://s2_read is the read enable signal from the S2 port on the Avalon bus module
.write (s2_write), file://s2_write is the write enable signal from the S2 port on the Avalon bus module
.schipselect (s2_chipselect), file://s2_chipselect is the chip select signal from the S2 port on the Avalon bus module
.address (s2_address), file://s2_address is the address from the S2 port on the Avalon bus module
.readdata (s_readdata), file://s2_chipselect is the 32-bit read data flowing to the S2 port on the Avalon bus module
.writedata (s2_writedata) file://s2_writedata is the 32-bit write data from the S2 port on the Avalon bus module
The software design goal of the startup scheme is that after the system is reset, during the process of transferring data from the external processor to the Nios II program memory and data memory, the operation of the Nios II processor is controlled by the external processor. When everything is ready, the external processor sends a command to release the Nios Ⅱ processor, and then the Nios Ⅱ processor can run normally.
The software part is mainly the code stored in the ROM in the startup delay module. This code mainly detects whether the 0th bit of the control register 2 in the startup delay module is 1. If it is 1, jump to the address stored in the control register 1 to execute. If the base address of the control register is CONTROL_REG_BASE, in order to reduce the amount of code, this code is easy to achieve with the assembly instructions of Nios II, and the code part is omitted here.
Finally, this solution was tested on a development board designed by ourselves, which can correctly complete the startup of Nios Ⅱ processor.
Although a multi-processor system can improve the performance of the system, traditional multi-processor systems generally only appear on workstations and high-end PCs. They are rarely used in embedded systems because of the high design cost. This paper designs a startup scheme for Nios Ⅱ soft core processor in a multiprocessor system. This scheme can control the startup of Nios Ⅱ processor when the external processor loads data into Nios Ⅱ program memory and data memory.
Implementation of Nios Ⅱ processor in HardCopy Ⅱ structured ASIC
Nios Ⅱ series embedded processors have three processor cores, which can realize a wide range of embedded processing applications. These soft IP processor cores can work on any latest-generation Altera FPGA and HardCopy® series of structured ASICs. Designers can choose to use high-performance cores, low-cost cores, or cost-effective cores. Nios Ⅱ series processors can achieve the following tasks:
Run real-time operating system as a system processor.
Share the load of existing processors
Perform I/O and data processing tasks
Accelerated digital signal processing (DSP) algorithm
When running in a HardCopy II structured ASIC, the superior processing power of the Nios II embedded processor meets the requirements of a high-performance system-on-chip (SOC). Nios Ⅱ embedded processor can provide system-level processor performance, and realize the integration of processor and system functions and logic in a single device. The combination of HardCopy II structured ASIC and Nios II embedded processor can meet the requirements of computing, mass storage, telecommunications and network applications.
Figure 1 is an example of multiple Nios II processors in a single HardCopy II structured ASIC for data processing and control applications.
Figure 1. Nios Ⅱ processor in HardCopy Ⅱ device for data processing
The HardCopy device design process allows designers to test and verify their designs in an FPGA. The verified design is then submitted to the HardCopy Design Center and implemented in a structured ASIC in a seamless migration without risk. HardCopy structured ASIC is the only device that can realize hardware function verification in FPGA and system software design and test in real system configuration environment before it is officially put into production.
Since the design was tested in FPGA before being handed over to Altera, Altera can guarantee to realize all the functions of the chip from the first prototype.
HardCopy Ⅱ structured ASIC architecture
The HardCopy Ⅱ structured ASIC is based on the Stratix Ⅱ series FPGA, and there are multiple prototype options between the HardCopy Ⅱ device and the Stratix Ⅱ FPGA. This depends on the required HardCopy device, I/O pins and packaging requirements. The HardCopy II device has a performance of up to 350-MHz, and achieves the highest performance to date with the Nios II processor core, while consuming only half of the power of the prototype Stratix II device.
The embedded DSP module in the Stratix Ⅱ device structure can also be used in HardCopy Ⅱ devices. These DSP modules are a perfect complement to the Nios II user instruction set and other hardware acceleration units. DSP designers can now generate DSP algorithms and complex mathematical programs in high-performance hardware DSP modules, which can be accessed as common software programs or run as user instructions for Nios II CPUs. Designers can easily and flexibly implement advanced software design and support parallel hardware operation performance in structured ASICs without the need for additional clock acceleration.
HardCopy Ⅱ device memory can meet all storage requirements of a typical SOC. Each maximum 9 M-RAM module can provide 64-K byte segments. The largest HardCopy II device contains 576 Kbytes of source code and data storage. The HardCopy Ⅱ structured ASIC also supports high-speed memory interfaces and can use the latest DDR2 SDRAM for external source code and data storage.
Low-cost licensing method
Nios Ⅱ series embedded processors are licensed as a one-time payment, without the need to pay additional royalties for each device or each project. The Nios II license allows the use of processor cores in any Altera device, so using Nios II processors and HardCopy II devices can provide the most cost-effective solution for mass production.
Nios II licenses are usually purchased as part of the Nios II development kit. Now it can be applied to Stratix, Stratix Ⅱ and Cyclone™ device series. The development includes Quartus Ⅱ FPGA design software and Nios Ⅱ integrated development environment and Nios Ⅱ license. All development kits include a development board and the required cables and power supplies. Users can use the Nios II processor for development and design within a few minutes after opening the package.
Altera's SOPC Builder automatic system development tool provides designers with a powerful development platform that can form a bus system composed of common systems including processors, peripherals, and memory interfaces.
The HardCopy Ⅱ design flow benefited from adopting the SOPC Builder module design method when FPGA design files were generated in the FPGA prototype stage. The module-based design method facilitates the integration of Nios II processor and other IP modules with typical high-density logic designs such as user logic, user instructions, and hardware accelerators.
The Nios Ⅱ Peripherals and Interface Library page has more details on peripherals suitable for Nios Ⅱ processors
Nios Ⅱ processor-the most common embedded processor in the world
Quickly build the most suitable processor system
The main challenge facing embedded developers is how to choose the most suitable processor, which will not exceed the budget in order to improve performance, and will not sacrifice functional features. The ideal embedded solution helps you:
Choose the CPU, peripherals and interfaces that best suit your application
On-site remote updates to maintain competition and meet changes in demand.
No need to change the design of the circuit board to improve performance-to accelerate the required functions.
Avoid the risk of processor and ASSP obsolescence
Implement multiple functions in one chip, reducing total cost, complexity and power consumption.
Through the most suitable CPU, peripherals and memory interfaces, as well as custom hardware accelerators to achieve the unique goal of each new design cycle, the Nios Ⅱ processor meets your needs with great flexibility.
If you are designing a Nios Ⅱ processor, the Nios Ⅱ Embedded Design Suite provides everything you need to develop reliable application software. With Eclipse-based Nios Ⅱ integrated development environment (IDE) and full software and operating system support, you will feel handy. Need to improve performance? No problem; use the Nios Ⅱ C2H compiler and simply right-click to speed up your ANSI C application.
The most popular configurable processor in the world
Nios II processors have shipped more than 15,000 development kits worldwide, and the world's top 20 OEMs have adopted the processor. Nios Ⅱ processor is currently the most popular configurable soft core processor. The Nios Ⅱ processor has great flexibility and is widely used. It achieves the best in characteristics, cost and performance. It is a processor that avoids the obsolescence of expensive products and helps you bring the product to the market as soon as possible.
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