D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits, and it is also an important unit circuit in digital logic circuits.
D flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits, and it is also an important unit circuit in digital logic circuits.
Therefore, D flip-flops are widely used in digital systems and computers. The flip-flop has two stable states, namely "0" and "1", which can be flipped from one stable state to another under the action of a certain external signal.
D flip-flops are composed of integrated flip-flops and gate circuits. There are two trigger modes: level trigger and edge trigger. The former can be triggered when CP (clock pulse)=1, and the latter is mostly triggered on the leading edge of CP (positive transition 0→1).
The second state of the D flip-flop depends on the state of the D terminal before the trigger, that is, the second state=D. Therefore, it has two functions setting 0 and setting 1.
For edge D flip-flops, since the circuit has a blocking effect during CP=1, the data state of the D terminal changes during CP=1 and will not affect the output state of the flip-flop.
D flip-flops are widely used and can be used as digital signal registers, shift registers, frequency divisions waveform generators, etc.
The D flip-flop consists of 4 NAND gates, among which G1 and G2 constitute the basic RS flip-flop. When level-triggered master-slave triggers work, the input signal must be added before the positive edge.
If there is an interference signal at the input during the CP high level, then it is possible to make the state of the flip-flop wrong. The edge trigger allows the input signal to be added immediately before the CP trigger edge. In this way, the time that the input terminal is disturbed is greatly shortened, and the possibility of being disturbed is reduced.
Edge D flip-flops are also called sustain-blocking edge D flip-flops. The edge D flip-flop can be formed by connecting two D flip-flops in series, but the CP of the first D flip-flop needs to be reversed with a NOT gate.
SD and RD are connected to the input terminals of the basic RS flip-flop. They are the preset and clear terminals respectively, and are active at a low level.
When SD=1 and RD=0 (the non-zero value of SD and the non-zero value of RD are 1, that is, the level value input from the outside in the two control ports, the reason is that the low level is effective), regardless of the input terminal D In each state, Q=0, Q not=1, that is, the flip-flop is set to 0; when SD=0 and RD=1 (SD is not 1, RD is not 0), Q=1, Q is not = 0, the flip-flop is set to 1, SD and RD are usually called directly set to 1 and set to 0.
We assume that they have all added high levels, which does not affect the operation of the circuit.
The working process is as follows:
1) When CP=0, NAND gates G3 and G4 are blocked, its output Q3=Q4=1, and the state of the flip-flop remains unchanged. At the same time, since the feedback signals of Q3 to Q5 and Q4 to Q6 open the two gates, the input signal D can be received, Q5=D, Q6=Q5 non=D non.
2) The flip-flop flips when CP changes from 0 to 1. At this time, G3 and G4 are turned on, and the status of their inputs Q3 and Q4 is determined by the output status of G5 and G6. Q3=Q5 non=D non, Q4=Q6 non=D. According to the logic function of the basic RS flip-flop, Q=Q3 not=D.
3) After the flip-flop flips, the input signal is blocked when CP=1. This is because after G3 and G4 are turned on, the states of their outputs Q3 and Q4 are complementary, that is, one of them must be 0. If Q3 is 0, the feedback line from G3 output to G5 input will block G5, which means it is blocked.
D is the path leading to the basic RS flip-flop; the feedback line plays the role of maintaining the flip-flop in the 1 state and preventing the flip-flop from turning into the 0 state, so the feedback line is called the set 1 maintenance line and the set 0 blocking line. When Q4 is 0, G3 and G6 are blocked, and the path from the D end to the basic RS trigger is also blocked.
The feedback line from the output of Q4 to G6 plays the role of maintaining the flip-flop in the 0 state, which is called the 0-set maintenance line; the feedback line from Q4 output to the G3 input plays a role in preventing the flip-flop from being set to 1, which is called the set 1 blocking line. Therefore, this trigger is often called a sustain-block trigger.
In short, the trigger accepts the input signal before the positive edge of CP and triggers the flip when the positive edge and the input are blocked after the positive edge. The three steps are completed after the positive edge, so it is called the edge trigger.
Compared with the master-slave flip-flop, the edge flip-flop of the same process has stronger anti-interference ability and higher working speed. /span>. According to the logic function of the basic RS flip-flop, Q=Q3 not=D.
Since the CP signal is applied to gates G3 and G4, the state of the output terminals of gates G5 and G6 must be established stably before the CP rising edge arrives. After the input signal reaches the D terminal, the output state of G5 can be established after the transmission delay time of the first-level gate circuit, and the output state of G6 needs to be established after the transmission delay time of the two-level gate circuit, so the input signal of the D terminal must be established first Arrived on the rising edge of CP, and the setup time should meet: tset≥2tpd.
In order to achieve edge triggering, it should be ensured that the output state of gate G5 remains unchanged during CP=1 and is not affected by the state change of the D terminal. For this reason, in the case of D=0, when the rising edge of CP arrives, it is necessary to wait for the low-level output by gate G3 to return to the input terminal of gate G5 before the low-level of the D terminal is allowed to change. Therefore, the hold time of the input low-level signal is tHL≥tpd. In the case of D=1, since the output of G4 will block G3 after the rising edge of CP arrives, the input signal is not required to remain unchanged, so the holding time of the input high-level signal tHH=0.
Calculated from the arrival of the CP rising edge, the output delay time tPHL from high to low and tPLH from low to high are respectively: tPHL=3tpdt PLH=2tpd.
In order to ensure that the synchronous RS flip-flop composed of gates G1～G4 can flip reliably, the duration of CP high level should be greater than tPHL, so the width of the high level of the clock signal tWH should be greater than tPHL.
In order to ensure that the new output levels of gates G5 and G6 are stably established before the next CP rising edge arrives, the duration of the CP low level should not be less than the sum of the transmission delay time of gate G4 and test, that is, the clock signal is low. The flat width tWL≥tset+tpd.
In the actual integrated flip-flop, the transmission time of each gate is different, and different forms of simplification have been made, so the results discussed above are just some qualitative physical concepts. The real parameters are determined by experiments.
When considering the establishment and holding time, the backward skew of the clock tree should be considered, and the forward skew of the clock tree should be considered when considering the establishment time. During post-simulation, the maximum delay is used to check the setup time, and the minimum delay is used to check the hold time.
The set-up time constraint is related to the clock cycle. When the system cannot work under a high-frequency clock, reducing the clock frequency can make the system complete its work. The hold time is a parameter that has nothing to do with the clock cycle. If the design is unreasonable and the place and route tool cannot deploy a high-quality clock tree, then no matter how the clock frequency is adjusted, the requirement cannot be met.
Only major changes to the designed system may work normally, resulting in a greatly reduced design efficiency. Therefore, a reasonable design system timing is the key to improving design quality. In programmable devices, the skew of the clock tree can hardly be considered, so the hold time is usually satisfactory.
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