This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > DEV_CLRn


I/O or global clear input. In QuartusII, if Enable Device-Wide Reset (DEV_CLRn) is selected. This pin is the global reset terminal. When this pin is set low, all registers will be cleared. This pin will not affect the boundary scan or programming operation of JTAG.


FPGA Tutorial Lattice FPGA
Need Help?


If you have any questions about the product and related issues, Please contact us.