I/O pin or open-drain output pin. When this pin is enabled, the low-to-high transition on this pin indicates that the FPGA has entered user mode. If the INIT_DONE output pin is enabled, this pin cannot be used as user I/O after configuration is complete. You can enable this pin in Quartus II by enabling the Enable INIT_DONE output option.
FPGA XC4000 Family 3K Gates 100 Cells 100MHz 5V 100-Pin PQFP
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
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