The ZPUino is a 32-bit processor running at 100Mhz with a library of Wishbone peripherals. Everything is controlled by a sketch and easy Arduino-style libraries. It is an Arduino-compatible Soft Processor on steroids!
The ZPUino is the ZPU soft processor adapted for use with the Arduino IDE and it was conceived of and developed by Alvaro Lopes.
32 bit soft processor running at 96Mhz.Uses a modified version of the Arduino IDE to load sketches.
Wishbone bus for connecting peripherals such as the following:
Actively maintained and developed by Alvaro Lopes.
The ZPUino is intended to make it easy to make System on Chip FPGA designs by adding Wishbone Peripherals to the ZPUino Wishbone slots. The RetroCade Synth is an example of a ZPUino System on Chip design.
The ZPUino uses a bootloader that bootstraps code from SPI Flash into internal Block Ram for the Papilio One and external SDRAM for the Papilio Pro. Every ZPUino variant has a special mode that allows code to be programmed to SPI Flash to be run at the next reset. The ZAP IDE sends a special command at a specific baud rate to trigger the programming mode. After the code is loaded to SPI Flash a reset is triggered and the bootloader shadows code from SPI FLash into the appropriate RAM location. This is why a ZPUino variant needs to be loaded to the Papilio board before a sketch is uploaded.
A ZPUino variant is a custom ZPUino System on Chip design that we have pre-synthesized for a specific purpose. It contains all of the Wishbone peripherals that will be useful for a specific task, such as VGA output. A ZPUino variant is normally named after a deity from Greek Mythology which roughly indicates what type of peripherals it includes. For example, the Hyperion variant includes the VGA peripheral and is named after Hyperion the "Lord of Light". Check out the ZPUino variant reference page to see all the pre-synthesized ZPUino variants that are currently available.
It is possible to speed up the process of writing sketches to the Papilio board by uploading them to RAM instead of SPI Flash. To do this hold down the left shift button while pressing the Upload icon. SmallFS files will not be updated and the code changes will not persist after a power down.
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA XC4000 Family 3K Gates 100 Cells 100MHz CMOS Technology 5V 120-Pin CPGA
FPGA XC3000 Family 4.5K Gates 224 Cells 135MHz 5V 160-Pin PQFP
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
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