EBR (Embedded Block RAM): RAM unit in ORCA Field Programmable Gate Array (FPGA), can be configured as RAM, read-only memory (ROM), first-in first-out (FIFO), content address memory (CAM )Wait.
With the rapid development and wide application of integrated circuits, a new IP soft core design method is proposed to improve the frequency of embedded block RAM in FPGA, which is based on the reusability of IP soft core. When the software processes the input data and different data type, it can obtain the required hardware resources and generate the corresponding hardware description language. In the design, the working frequency is improved in limited hardware resources through optimizing the data preprocessing method and changing the result of the layout. The designed IP soft core has been verified by functional simulation, and the experiment result has shown that it can meet the functional and performance requirements, and the working frequency can be increased by 25.56%.
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA XC4000 Family 3K Gates 100 Cells 100MHz CMOS Technology 5V 120-Pin CPGA
FPGA XC3000 Family 4.5K Gates 224 Cells 135MHz 5V 160-Pin PQFP
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
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