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HDMI(High Definition Multimedia Interface) is a fully digital video and sound transmission interface, which can send uncompressed audio and video signals. HDMI can be used for set-top boxes, DVD players, personal computers, TV games, integrated amplifiers, digital audio, and televisions. HDMI can send audio and video signals at the same time. Because the audio and video signals use the same wire, it greatly simplifies the installation difficulty of the system lines.


Brief description

HDMI is designed to replace the older analog signal audio and video transmission interface such as SCART or RCA and other terminals. It supports various TV and computer video formats, including SDTV, HDTV video images, plus multi-channel digital audio. Both HDMI and UDI without the audio transmission function inherit the core technology of DVI "Transmit Minimized Differential Signaling" TMDS, which is still essentially an extension of DVI. The video content of DVI, HDMI, UDI is transmitted in an instant, dedicated line mode, which can ensure that there is no jamming when the video traffic is large. The amount of data per pixel is 24 bits. Timing and VGA signals are very similar. The picture is sent line by line, and a specific blank time (similar to an analog scan line) is added after each line and frame are sent, and the data is not "Micro-Packet Architecture" It will not only update the changed parts of the two frames before and after. Each picture will be completely resent when the update is made. When the specification was first formulated, the maximum pixel transfer rate was 165Mpx/sec, which was sufficient to support 60 frames per second in 1080p quality, or UXGA resolution (1600x1200); it was later expanded to 340Mpx/sec in the HDMI 1.3 specification to match future possibilities Demand.

DisplayPort was originally developed for liquid crystal displays, using the "Micro-Packet Architecture" transmission architecture, and video content is transmitted in packets, which is obviously different from video transmission technologies such as DVI and HDMI. That is to say, the emergence of HDMI replaces analog signal video, and the emergence of DisplayPort replaces the DVI and VGA interfaces.

HDMI also supports uncompressed 8-channel digital audio transmission (sampling rate 192kHz, data length 24bits/sample), and any compressed audio stream such as Dolby Digital or DTS, and also supports the 8-channel 1bit DSD signal used by SACD. In the HDMI 1.3 specification, ultra-high data volume uncompressed audio streams such as Dolby TrueHD and DTS-HD are added.

Standard Type A HDMI connector has 19 pins, and another that supports higher resolution Type B connector is defined it, but there is still no use of any vendor Type B connector. The Type B connector has 29 pins, allowing it to send an extended video channel to meet future high image quality requirements, such as WQSXGA (3200x2048).

Type A HDMI is backward compatible with the Single-link DVI-D or DVI-I interface used by most monitors and graphics cards today (but does not support DVI-A), which means that the signal source using the DVI-D interface can pass through the conversion cable Drive HDMI display, but this conversion scheme does not support audio transmission and remote control function. In addition, if there is no HDCP certified DVI display, it will not be able to watch the video data with HDCP encryption protection output from HDMI (all HDMI displays support HDCP, but most monitors with DVI interface do not support HDCP), Type B HDMI connector It will also be backward compatible with the Dual-link DVI interface.

The sponsors of the HDMI organization include major manufacturers of consumer electronics products, such as Hitachi, Panasonic, Quasar, Philips, Sony, Thomson RCA, Toshiba, Silicon Image. Digital Content Protection, LLC provides copy protection technology related to the HDMI interface. In addition, HDMI is also supported by major film production companies such as 20th Century Fox, Warner Bros., Disney, major consumer electronics manufacturers including Samsung Electronics, and multiple cable TV system operators.

The connector

The standard HDMI connector is called "type A" and has 19 pins. Out of the 19 pins, 8 are of particular interest as they form 4 TMDS differential pairs to transport the actual high-speed video info.

TMDS clock+ and clock-

TMDS data0+ and data0-

TMDS data1+ and data1-

TMDS data2+ and data2-


Our connection from an FPGA to an HDMI connector can hardly be simpler... we use 8 FPGA pins configured as 4 differential TMDS outputs.


Video signal

Let's create a 640x480 RGB 24bpp @ 60Hz video signal. That's 307200 pixels per frame, and since each pixel has 24 bits (8 bits for red, green and blue), at 60Hz, the HDMI link transports 0.44Gbps of "useful" data.

But video signals usually also have an "off-screen" area, which is used by the HDMI receiver (TV or monitor) for some housekeeping. Our 640x480 frame is actually sent as an 800x525 frame.


With that in mind, we need a 24.5MHz pixel clock to achieve 60 frames per seconds, but HDMI specifies a 25MHz minimum pixel clock, so that's we use (which gets us a 61Hz frame rate).

TMDS signals

The FPGA has 4 TMDS differential pairs to drive.
First, the TMDS clock is simply the pixel clock, so it runs at 25MHz. The other 3 pairs transmit the red, green and blue signals, so we get something like that.

Things are in fact just a bit more complicated. HDMI requires that we scramble the data and add 2 bits per color lane, so we have 10 bits instead of 8 and the link ends up transporting 30 bits per pixel. The scrambling and extra bits are needed by the HDMI receiver to properly synchronize to and acquire each lane - more details in the DVI and HDMI specifications.

Source code

First a video generator. We use a couple of counters that go through an 800x525 pixel area...

reg [9:0] CounterX;  // counts from 0 to 799
always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;reg [9:0] CounterY;  // counts from 0 to 524
always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;

and create the h-sync and v-sync signals...

wire hSync = (CounterX>=656) && (CounterX<752);
wire vSync = (CounterY>=490) && (CounterY<492);
wire DrawArea = (CounterX<640) && (CounterY<480);

and generate some red, green and blue signals (8 bits each)...

wire [7:0] red = {CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00};
wire [7:0] green = CounterX[7:0] & {8{CounterY[6]}};
wire [7:0] blue = CounterY[7:0];

which are expanded to 10 bits each through three "TMDS_encoder" instances.

wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .TMDS(TMDS_red)  , .CD(2'b00)        , .VDE(DrawArea));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .TMDS(TMDS_green), .CD(2'b00)        , .VDE(DrawArea));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .TMDS(TMDS_blue) , .CD({vSync,hSync}), .VDE(DrawArea));

Now, we have three 10 bits values to be sent for every pixel clock period. We multiply the 25MHz clock by 10 to generate a 250MHz clock...

DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1'b0));

and use three shift registers clocked at 250MHz...

reg [3:0] TMDS_mod10;  // modulus 10 counter
always @(posedge clk_TMDS) TMDS_mod10 <= (TMDS_mod10==9) ? 0 : TMDS_mod10+1;
reg TMDS_shift_load;
always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==9);
reg [9:0] TMDS_shift_red, TMDS_shift_green, TMDS_shift_blue;
always @(posedge clk_TMDS)
    TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];
    TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
    TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1];	

to send the TMDS data outside the FPGA.

OBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));
OBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));
OBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));
OBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));

Higher resolutions

With 640x480, we used 250MHz clocked serializers, but for higher resolutions, we need higher frequencies, which can quickly go above the ability of FPGAs. The workaround is to use some special FPGA IO features, like DDR outputs and IO serializers.

Another problem at higher frequencies is how to reliably transfer data from the pixel clock domain to the serializer domain. One possible technique is to use a shallow FIFO. Check the Xilinx XAPP460 (for Spartan-3A) and XAPP495 (for Spartan-6) application notes to get some ideas.


Here are a few shots made using a digital camera shooting an LCD monitor driven by Pluto-IIx HDMI.



FPGA Tutorial Lattice FPGA
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