A combinatorial path which starts at an input of the chip and ends at an output of the chip. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal.
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA XC4000 Family 3K Gates 100 Cells 111MHz 5V 100-Pin PQFP
Spartan and Spartan-XL Families Field Programmable Gate Arrays
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