A Xilinx® primitive which is basically used for clock management. Global clock buffer is gated with a clockenable signal. If clock enable is disabled the clock will also be disabled.
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA XC3000 Family 4.5K Gates 224 Cells 70MHz 5V 132-Pin CPGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA
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