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Vivado Design Suite is an integrated design environment released by FPGA manufacturer Xilinx in 2012. Including a highly integrated design environment and a new generation of tools from the system to the IC level, these are based on a shared scalable data model and a common debugging environment. It is also an open based on the AMBA AXI4 interconnect specification, IP-XACT IP package metadata, tool command language (TCL), Synopsys system constraints (SDC), and other industry standards that help tailor the design process to customer needs and meet industry standards surroundings. The Vivado tool built by Xilinx combines various programmable technologies and can expand the design of up to 100 million equivalent ASIC gates.



Focus on integrated components-In order to solve the integration bottleneck problem, Vivado Design Suite uses ESL design for rapid synthesis and verification of C language algorithm IP, standard algorithms for reuse and RTL IP packaging technology, standard IP packaging and various types The system integration of the system building blocks increases the simulation speed of module and system verification by 3 times, and at the same time, the performance of hardware co-simulation increases by 100 times.

Components focused on implementation-In order to solve the bottleneck of implementation, the Vivado tool uses a hierarchical device editor and layout planner, which is 3 to 15 times faster, and provides SystemVerilog with the industry's best supported logic synthesis tool, speed increase 4 times more deterministic placement and routing engine, and “cost” functions that can minimize multiple variables such as timing, line length, and route congestion through analysis techniques. In addition, the incremental process allows any changes to the engineering change notice (ECO) to be processed quickly by reimplementing only a small part of the design, while ensuring that performance is not affected. Finally, the Vivado tool can estimate the power consumption, timing, and occupied area of each stage of the design process by using the latest shared scalable data model, so as to achieve pre-analysis, and then optimize integrated functions such as automated clock gates.

Common problem

Why create a new tool kit instead of upgrading the design kit?

Customers need a new design environment to increase productivity, shorten time to market, go beyond programmable logic, and implement programmable system integration. In response to customer needs, Xilinx engineers began to take action in 2008 to create the pinnacle of Vivado tools.

What are the major challenges facing designers today that Vivado tools can solve?

"All-Programmable" devices not only cover programmable logic design, but also involve programmable system integration, to integrate more and more system functions on fewer chips. In order to build the above system, we will face a series of new integration and implementation design productivity bottlenecks. This is a problem we must solve: integration bottleneck, integrated C language algorithm and RTL-level IP, mixed DSP, embedded, connection function, logic Domain, module and "system" verification, design and IP reuse, implementation bottlenecks, hierarchical chip layout planning and zoning, multi-domain and multi-chip physical optimization, multi-variable "design" and "timing" convergence conflicts, late in design Chain reaction caused by ECO and change

What advantages does the latest environment have over the productivity of Design Suite 14?

Alliance program members, customers, and Xilinx teams have run various field-tested designs, and the results show that the Vivado Design Suite increases overall integration and implementation speed by a factor of four compared to competing tools.

Does Xilinx no longer need the ISE design kit?

No. Version 14 of the ISE Design Suite supports current 28nm products, and Xilinx will continue to provide support for tools designed for previous generation products.

What can customers do now?

Customers can sign up for the early trial program, download related technical documents, be the first to learn about the Vivado Design Suite, and prepare for their first or next 7 series FPGA and Zynq-7000 EPP design. The 7 Series was launched to the public earlier this summer, and the Zynq-7000 EPP will be shipped to the public later this year. Early trial program participants can download the tools on May 8.

What exactly does "All-Programmable" device mean?

For the 28nm process, Xilinx has developed many types of programmable technologies, from logic and IO, software programmable ARM processing systems, 3D-IC, analog mixed signal (AMS), systems to IC design tools and IP, etc. . Xilinx combines the above programmable technologies in different combinations and then integrates them into "All-Programmable" devices, such as the currently shipped Virtex-7 2000T FPGA and Zynq-7000 based on stacked silicon interconnect technology (SSIT) scalable processing Platform (EPP) and FPGA supporting advanced analog mixed signal (AMS), high-performance SERDES and PLL to programmable data converter resources.

What can the Vivado Design Suite help customers achieve before?

When designers use next-generation "All-Programmable" devices to implement programmable logic or programmable system integration in many applications such as automotive, consumer, industrial control, wired and wireless communications, and medical, Vivado tools help improve their Productivity. Especially for a new generation of design, as mentioned above, engineers can use Vivado tools to solve many productivity bottlenecks in integration and implementation.

Is it difficult to learn to use the Vivado Design Suite?

Learning to use the button-type Vivado integrated development environment (IDE) should be relatively simple for most users, especially if users already have experience in using the ISE PlanAhead tool, it will be easier. As users continue to become familiar with the Vivado IDE, they can also take advantage of new features that are constantly being introduced and the analysis and optimization functions built into the GUI to easily optimize performance, power consumption, and resource utilization.

Does it support some reconfigurable functions?

stand by. Some reconfigurable features are available in the beta version at the end of 2012. In 2012, users who need some reconfigurable functions will need to continue to use ISE.

How is Vivado Integrated Technology different from Xilinx Integrated Technology (XST)?

Vivado synthesis technology is based on industry-proven ASIC synthesis technology, which can be extended to adapt to very large designs. It can support SystemVerilog, SDC, TCL, etc., and uses the scalable data model shared by Vivado to support cross-testing of the entire process.

Can the new tool and ISE support the migration of the project?

ISE project browser and PlanAhead project can be ported to Vivado IDE, but Vivado project cannot be ported to PlanAhead. In addition to the constraint file, all other project settings including the source file list can be transferred. Customers must create constraints in Xilinx Design Constraint (XDC) format and add them separately to the project.

Why is Vivado IP Integrator better than QSys?

Designers can use Vivado to create IP systems in the form of graphics, or use TCL, parameter transfer, Vivado simulation and ChipScope integration, etc., specifically designed for debugging. Cross-testing returning to IPI from implementation tools (reports, layout planning, schematics) can accelerate integration, which is also a big advantage.

How is the Vivado emulator different?

The Vivado emulator uses a brand new engine and is tightly integrated into the Vivado IDE. The engine is three times faster than ISim, but only consumes half the memory capacity. It is fully integrated in the Vivado IDE and can better control the operation of the emulator through TCL.

Can the Vivado emulator make the old architecture design meet the 7 series requirements?

Generally speaking, Xilinx recommends that users adopt a native architecture. However, Vivado supports the old architecture to the same extent as ISE supports all Virtex-level devices.

Does the Vivado simulator support VHDL and Verilog timing simulation?

Vivado only supports Verilog's timing simulation. But Vivado can provide functional simulation support for Verilog and VHDL and mixed languages.

Why doesn't Vivado support VHDL timing simulation?

VHDL timing simulation is based on VITAL simulation. This standard is very slow, restrictive, and has not been updated for a long time.

Can customers compile Xilinx simulation libraries with Mentor, Synopsys, Cadence and Aldec?

can. The Vivado Design Suite provides a TCL command called compxlib to compile the simulation library.

Does the Vivado simulator support SystemVerilog or hardware co-simulation?

We plan to support both in future software releases.


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