The watchdog timer (WDT, Watch Dog Timer) is an integral part of the single-chip microcomputer, it is actually a counter, generally give the watchdog a number, the watchdog starts counting after the program starts running. If the program runs normally, after a while, the CPU should issue an instruction to set the watchdog to zero and restart counting. If the watchdog increases to the set value, it is considered that the program does not work normally, forcing the entire system to reset.
When used, WDT will increment until it overflows, or "time out". Unless in Sleep or Idle mode, a WDT time-out will force the device to reset. To avoid WDT time-out reset, the user must periodically clear the watchdog timer with PWRSAV or CLRWDT instructions. If the WDT times out in Sleep or Idle mode, the device will wake up and continue code execution from where the PWRSAV instruction was executed. In both of the above cases, the WDTO bit (RCON<4>) will be set, indicating that the device reset or wake-up event is caused by a WDT time-out. If the WDT wakes the CPU from Sleep or Idle mode, the "Sleep" status bit (RCON<3>) or "Idle" status bit (RCON<2>) will also be set, indicating that the device was previously in power saving mode.
During normal operation, a WDT time-out will generate a device reset. When the device is in sleep state, a WDT time-out will wake up the device to continue normal operation (called WDT wake-up). Clearing the WDTE setting bit can permanently turn off the WDT.
The postscaler assignment is completely controlled by software, that is, it can be changed at any time during program execution.
To avoid unpredictable device resets, when changing from the Timer0 prescaler assignment to the WDT postscaler assignment, the following instruction sequence must be executed. Even if WDT is disabled, this instruction sequence must be executed.
The watchdog timer is an integral part of the single-chip microcomputer, and has important significance in the debugging and running of the single-chip microcomputer program. Its main function is to reset the microcontroller by resetting the device if the software fails (if the software does not clear the device). It can also be used to wake up the device from sleep or idle mode. The watchdog timer provides an independent protection system for the microcontroller. When the system fails, after a selectable timeout period, the watchdog will use the RESET signal In response, options such as x25045 have three timeout periods: 1.4 seconds, 600 milliseconds, and 200 milliseconds. When your program crashes, x25045 will reset the microcontroller.
Most watchdog timer ICs produce a single, limited output pulse duration when the watchdog times out. This is suitable for triggering a reset or interrupting the microprocessor, but some applications require a latch for output (fault indicator).
Considering safety issues, automotive electronic systems require monitoring circuits to monitor fault tolerance or safety. The watchdog timer can ideally meet such needs. By detecting the periodic pulses generated under the normal operating conditions of the microcontroller, the failure state of the circuit or IC is detected, and once a failure occurs, it can be immediately switched to the backup/redundant system.
The watchdog timer is a timer circuit. It generally has an input called kicking the dog or service the dog, and an output to the RST end of the MCU. When the MCU is working normally, every interval Time to output a signal to the dog feeding terminal to clear the WDT.If the dog is not fed for more than the specified time, (generally when the program runs away), when the WDT timing exceeds, a reset signal will be given to the MCU to reset the MCU. Prevent MCU crash. The role of watchdog is to prevent the program from looping, or run away. In consideration of real-time monitoring of the operating state of the single-chip microcomputer, a chip specifically for monitoring the running state of the single-chip microcomputer program, commonly known as the "watchdog" (watchdog) integrated circuit (MAX*9), was produced. Provides an indication of a fault in the input pulse stream loss latch response. The circuit can monitor the fan (calculation of the output speed of the upper fan), an oscillation circuit, or a microprocessor software implementation.
A simple circuit (Figure 1) provides an indication of the response to input pulse flow loss latch failure. Based on the μP-supervisor/watchdog integrated circuit (MAX*9), this circuit is used to monitor the fan (calculated at the fan speed output), an oscillation circuit, or a suitable microprocessor software to execute.
During power-up, the active low reset remains low until the VCC stabilizes and the reset timeout expires. The capacitor C passes through R until the gate voltage of the FET reaches the threshold (voltage VTH), which turns on the field effect transistor to enable the latching capability. To prevent false triggering, you should set the RC delay time to far exceed the reset timeout.
The WDI input (pin 6) must be set to the lowest rate by the switching capacitor CSWT. If this does not happen, the active low reset becomes low, and the LED indicator resets after connecting and pulling low, thereby locking the low reset. The circuit remains active until you cycle VCC or push the switch in this condition. Either turn off the FET action and allow the reset to go high.
In order to monitor the fan's open-drain speed measurement signal, connect a 10kΩ pull-up resistor from the world development indicator 10kΩ to VCC (pin 8). Since the fan needs some time to spin up, the watchdog circuit needs to be disabled for a short delay interval. You can reset this delay capacitor (C2) from ground. Please note that this delay must be less than the RC delay mentioned above, or the active low reset latch will be shorter too early.
For a fan monitor, set the maximum speed pulse period for the CSWT value according to the formula 5.07×106×CSWT, where CSWT is within a few seconds. If the speed is lower than this threshold, the low level effectively resets the output low and latch.
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