Universal asynchronous receiver/transmitter (Universal Asynchronous Receiver/Transmitter), usually called UART. It converts the data to be transmitted between serial communication and parallel communication. As a chip that converts parallel input signals into serial output signals, the UART is usually integrated into the connection of other communication interfaces.
The concrete object appears as an independent modular chip or as a peripheral device integrated in a microprocessor. It is generally of RS-232C specifications, and is used in conjunction with standard signal amplitude conversion chips like Maxim's MAX232 to serve as an interface to external devices. A product that adds a synchronous serial signal conversion circuit to the UART is called USART (Universal Synchronous Asynchronous Receiver Transmitter).
UART is a universal serial data bus used for asynchronous communication. The two-way communication of the bus can realize full-duplex transmission and reception. In the embedded design, the UART is used for communication between the host and auxiliary equipment, such as the communication between the car audio and the external AP, and the communication with the PC includes communication with the monitor debugger and other devices, such as EEPROM.
As a kind of asynchronous serial communication protocol, UART works by transmitting each character of the transmitted data bit by bit.
The meaning of each of them is as follows:
Start bit: A logical "0" signal is sent out first, indicating the beginning of the transmitted character.
Data bit: immediately after the start bit. The number of data bits can be 4, 5, 6, 7, 8, etc., forming a character. Usually use ASCII code. The transmission starts from the lowest bit and is located by the clock.
Parity bit: After adding this bit to the data bit, the number of "1"s should be even (even parity) or odd (odd parity) to verify the correctness of data transmission.
Stop bit: It is the end mark of a character data. It can be a high level of 1 bit, 1.5 bits, and 2 bits. Since the data is timed on the transmission line, and each device has its own clock, it is likely that there is a small out-of-sync between the two devices in the communication. Therefore, the stop bit not only indicates the end of the transmission, but also provides an opportunity for the computer to correct clock synchronization. The more bits that are suitable for stop bits, the greater the tolerance of different clock synchronization, but the slower the data transmission rate.
Idle bit: in logic "1" state, indicating that there is no data transmission on the current line.
Baud rate: It is an index to measure the data transmission rate. Represents the number of symbols transmitted per second (symbol). The amount of information (number of bits) represented by a symbol is related to the order of the symbol. For example, the transmission uses 256 order symbols, each 8bit represents a symbol, the data transmission rate is 120 characters/second, then the baud rate is 120baud, and the bit rate is 120*8=960bit/s. The concepts of these two are easy to get wrong.
⑴ Output buffer register, which receives the parallel data sent by the CPU from the data bus and saves it.
⑵ Output shift register, which receives the parallel data sent from the output buffer, shifts the data out at the rate of the sending clock, that is, converts the parallel data into serial data output.
(3) Input shift register, which shifts the data appearing on the serial data input line one by one at the rate of receiving the clock. When the data is full, it is sent to the input buffer register in parallel, that is, the serial data is converted into parallel data.
⑷ Input buffer register, which receives parallel data from the input shift register, and then is taken away by the CPU.
⑸Control register, it receives the control word sent by the CPU, and the content of the control word determines the transmission mode and data format during communication. For example, whether to use asynchronous mode or synchronous mode, the number of data characters, the presence or absence of parity, odd or even parity, the number of stop bits and other parameters.
⑹ Status register. The status register stores various status information of the interface, such as whether the output buffer is empty and whether input characters are ready. During the communication process, when a certain state is met, the state detection logic in the interface sets the corresponding position of the state register to "1" to allow the CPU to query.
The transmit logic performs "parallel→serial" conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream with the start bit first, and according to the programmed configuration in the control register, it is immediately followed by the data bit (note: the least significant bit LSB is output first), the parity bit, and the stop bit.
After detecting a valid start pulse, the receiving logic performs a "serial → parallel" conversion on the received bit stream. In addition, overflow errors, parity errors, framing errors, and line-break errors are detected, and the detected status is appended to the data written to the receive FIFO.
The baud rate divisor (baud-rate divisor) is a 22-digit number, which consists of a 16-bit integer and 6 decimal places. The baud rate generator uses the number composed of these two values to determine the bit period. With a divider with a fractional baud rate, at a sufficiently high system clock rate, the UART can generate all standard baud rates with little error.
When sending, data is written to the transmit FIFO. If the UART is enabled, it will start sending data according to the preset parameters (baud rate, data bits, stop bits, parity bits, etc.) until there is no data in the transmit FIFO. Once data is written to the transmit FIFO (if the FIFO is not empty), the BUSY busy flag bit BUSY is valid and remains valid during the data transmission. The BUSY bit becomes invalid only when the transmit FIFO is empty and the last character has been sent from the shift register, including the stop bit. Even if the UART is no longer enabled, it can also indicate busy status. The relevant library function of the BUSY bit is UARTBusy()
When the UART receiver is idle, if the data input becomes "low", that is, the start bit is received, the reception counter starts to run, and the data is sampled in the 8th cycle of Baud16. If Rx is still low in the 8th cycle of Baud16, the start bit is valid, otherwise it will be regarded as an erroneous start bit and ignored.
If the start bit is valid, consecutive data bits are sampled every 16th cycle of Baud16 (that is, after one bit cycle) according to the length of the data character being programmed. If parity mode is enabled, the parity bit is also detected.
Finally, if Rx is high, the valid stop bit is confirmed, otherwise a frame error occurs. When a complete character is received, the data is stored in the receive FIFO.
The UART can generate an interrupt when the following conditions occur:
FIFO overflow error
Line abort error (line-break, that is, the state where the Rx signal is always 0, including parity and stop bits)
Frame error (stop bit is not 1)
Receive timeout (receive FIFO has data but not full, and subsequent data will not come for a long time)
Since all interrupt events will be ORed together before being sent to the interrupt controller, the UART can only generate an interrupt request to the interrupt at any time. By querying the interrupt status function UARTIntStatus( ), the software can handle multiple interrupt events (multiple parallel if statements) in the same interrupt service function.
FIFO is the abbreviation of "First-In First-Out", which means "First In First Out", and is a common queue operation. The UART module of Stellaris series ARM contains two 16-byte FIFOs: one for sending and the other for receiving. The two FIFOs can be configured to trigger interrupts at different depths. Available configurations include: 1/8, 1/4, 1/2, 3/4, and 7/8 depth. For example, if the receive FIFO selects 1/4, a receive interrupt is generated when the UART receives 4 data.
The basic working process of the transmit FIFO: As long as there is data filled in the transmit FIFO, the sending process will be started immediately. Since sending itself is a relatively slow process, other data that needs to be sent can continue to be filled into the send FIFO while sending. When the transmit FIFO is full, it can no longer be filled, otherwise it will cause data loss, at this time you can only wait. This wait will not be long. Taking the baud rate of 9600 as an example, the time to wait for a vacancy to appear is around 1ms. The transmit FIFO will send the data out one by one in the order in which the data is filled until the transmit FIFO is completely empty. The data that has been sent will be automatically cleared, and there will be one more empty slot in the transmit FIFO.
The basic working process of the receive FIFO: When the hardware logic receives the data, it will fill the received FIFO with the received data. The program should remove these data in time. The data is also automatically deleted in the receive FIFO, so there will be one more empty space in the receive FIFO at the same time. If the data in the receive FIFO is not taken away in time and the receive FIFO is full, the data will be lost when there is no empty space to fill when the data is received later.
The transceiver FIFO is mainly introduced to solve the problem that the UART transceiver interrupt is too frequent and the CPU efficiency is not high. When performing UART communication, the interrupt method is simpler and more efficient than the polling method. However, if there is no transceiver FIFO, the processing will be interrupted every time a data is sent and received, and the efficiency is still not high enough. If you have a transceiver FIFO, you can send and receive several data (up to 14) in a row and then generate an interrupt and then process it together, which greatly improves the efficiency of sending and receiving.
There is no need to worry about the problem of data loss or failure to be processed in time due to the FIFO mechanism, because it has helped you think of any problems in the sending and receiving process, as long as the UART is initialized and configured, you can safely send and receive, FIFO And the interrupt routine will do everything automatically.
The UART can enter an internal loopback mode for diagnosis or debugging. In loopback mode, the data sent from Tx will be received by the Rx input.
In some Stellaris series ARM chips, the UART also contains an IrDA serial infrared (SIR) encoder/decoder module. The function of IrDA SIR module is to convert between asynchronous UART data stream and half-duplex serial SIR interface. No analog processing operations are performed on-chip. The task of the SIR module is to provide a digitally encoded output and a decoded input to the UART. The UART signal pin can be connected with an infrared transceiver to realize IrDA SIR physical layer connection.
It is used to control the CPU and the rest of the message transmission during the mobile phone design and test phase.
UART is the abbreviation of universal asynchronous transceiver (asynchronous serial communication port), which includes RS232, RS449, RS423, RS422 and RS485 interface standard specifications and bus standard specifications, that is, UART is the general name of asynchronous serial communication port. And RS232, RS449, RS423, RS422 and RS485, etc., are the interface standards and bus standards corresponding to various asynchronous serial communication ports. It specifies the electrical characteristics, transmission rate, connection characteristics and mechanical characteristics of the interface of the communication port. In fact, it belongs to the concept of physical layer in the communication network and has no direct relationship with the communication protocol. The communication protocol belongs to the concept of Data Link Layer in the communication network. COM is short for asynchronous serial communication port on PC (personal computer). For historical reasons, IBM's PC external interface is configured as RS232, becoming the de facto default standard in the PC world. Therefore, the COM of the PC is now RS232. If equipped with multiple asynchronous serial communication ports, they are called COM1, COM2...
Data transmission can start with the least significant bit (LSB) first. However, some UARTs allow the flexibility to send the least significant bit or the most significant bit (MSB) first.
The UART in the microcontroller transfers data at speeds ranging from a few hundred bits per second to 1.5Mb. For example, the speed of high-speed UART communication embedded in the ElanSC520 microcontroller can be as high as 1.152Mbps. The UART baud rate is also affected by the distance (line length) of the transmitting and receiving lines.
There are two types of hardware on the market that only support asynchronous communication and support both asynchronous and synchronous communication. The former is the meaning of the UART name itself, which is called the serial communication interface (SCI) in Motorola microcontrollers; the Universal Synchronous Asynchronous Transceiver (USART) in Microchip microcontrollers and the UART in Fujitsu microcontrollers are the latter Two typical examples of the author.
The UART first converts the received parallel data into serial data for transmission. The message frame starts from a low-order start bit, followed by 5~8 data bits, an available parity bit and one or several high-order stop bits. When the receiver finds the start bit, it knows that the data is ready to send and attempts to synchronize with the transmitter clock frequency. If parity is selected, the UART adds a parity bit after the data bit. Parity bits can be used to help error checking.
During the reception process, the UART removes the start bit and end bit from the message frame, performs parity check on the incoming bytes, and converts the data bytes from serial to parallel. The UART also generates additional signals to indicate the status of transmission and reception. For example, if a parity error occurs, the UART sets the parity flag. The parity bit is used to verify that the transmission is correct.
UART is the key part of serial communication port in computer. In a computer, the UART is connected to a circuit that produces signals that are compatible with RS232 specifications. The RS232 standard defines a logic "1" signal from ground to -3 to -15 volts, and a logic "0" from ground to +3 to +15 volts. Therefore, when the UART in a microcontroller is connected to a PC, it needs an RS232 driver to switch the level.
Uart here refers to the serial port with TTL level; RS232 refers to the serial port with RS232 level.
TTL level is 5V, and RS232 is a negative logic level, which defines +5~+12V as low level, and -12~-5V as high level.
The RXD and TXD of the Uart serial port are generally directly connected to the pins of the processor chip, while the RXD and TXD of the RS232 serial port generally need to undergo level conversion (usually level conversion by a chip such as Max232) to be connected to the processor chip. Otherwise, such a high voltage may burn the chip.
The serial port of the computer we usually use is RS232. When we are doing circuit work, we should pay attention to whether the serial port of the peripheral is Uart type or RS232 type. If it does not match, we should find a conversion line (usually this conversion line There is a chip similar to Max232 for level conversion), but you can't blindly connect the two serial ports.
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 208-Pin HSPQFP EP
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 665-Pin FCBGA