Synchronous dynamic random-access memory (SDRAM) is a dynamic random-access memory (DRAM) with a synchronous interface. Usually DRAM has an asynchronous interface, so that it can respond to changes in control input at any time. SDRAM has a synchronous interface, which will wait for a clock signal before responding to control input, so that it can be synchronized with the computer's system bus. The clock is used to drive a finite state machine to pipeline the incoming instructions. This allows SDRAM to have a more complex operating mode than asynchronous DRAM (synchronous DRAM) without a synchronous interface.
Pipeline means that the chip can accept a new instruction before processing the previous instruction. In a write pipeline, the write command can be executed immediately after the execution of another instruction without waiting for the time for data to be written to the storage queue. In a read pipeline, the required data arrives after a fixed number of clock frequencies after the read command is issued, and this waiting process can issue other additional commands. This delay is called latency and is an important parameter when buying memory for a computer.
SDRAM is widely used in computers, from the initial SDRAM to the next generation of DDR (or DDR1), then DDR2 and DDR3 entered the mass market, and DDR4 entered the consumer market in 2015.
SDRAM has experienced five generations from development to the present, namely: first-generation SDR SDRAM, second-generation DDR SDRAM, third-generation DDR2 SDRAM, fourth-generation DDR3 SDRAM, fifth-generation, DDR4 SDRAM.
The first-generation SDRAM uses a single-ended (Single-Ended) clock signal. The second-generation, third-generation, and fourth-generation clocks use a differential clock signal that can reduce interference as a synchronous clock because the operating frequency is relatively fast.
The clock frequency of SDR SDRAM is the frequency of data storage. The first-generation memory is named after the clock frequency, such as pc100, pc133 indicates that the clock signal is 100 or 133MHz, and the data read and write rate is also 100 or 133MHz.
The second, third, and fourth generation DDR (Double Data Rate) memory uses the data reading and writing rate as the naming standard, and the symbol indicating its DDR algebra is added in front, PC-that is DDR, PC2=DDR2, PC3=DDR3 . If PC2700 is DDR333, its working frequency is 333/2=166MHz, 2700 means the bandwidth is 2.7G.
DDR read and write frequency from DDR200 to DDR400, DDR2 from DDR2-400 to DDR2-800, DDR3 from DDR3-800 to DDR3-1600.
Many people misunderstand SDRAM as the first generation, that is, SDR SDRAM, and interpret it as a term, which is misleading.
SDR is not equal to SDRAM.
Pin: The metal pin used to connect the module or chip to an external circuit, and the pin of the module is often called the "gold finger".
SIMM: Single In-line Memory Module, single-row memory module. The memory module is what we often say, the so-called single row means that the interface between the module circuit board and the motherboard slot has only one row of pins (although there are gold fingers on both sides).
DIMM: Double In-line Memory Module. It is our common type of module. The so-called double row means that the interface between the module circuit board and the motherboard slot has two rows of pins, and the gold fingers on both sides of the module circuit board correspond to a row of pins.
RIMM: Registered DIMM, a two-wire memory module with registers, this memory slot can only be inserted into DDR or Rambus memory.
SO-DIMM: Memory modules commonly used in notebooks.
The gold fingers of SDRSDRAM memory modules are usually 168 lines, while the gold fingers of DDR SDRAM memory modules are usually 184 lines.
The number of notches and the position of the notches of the gold fingers of several generations of products are also different to effectively prevent reverse insertion and wrong insertion. SDR SDRAM has two notches and DDR only has one notch.
1. Main timing parameters affecting performance
The so-called performance impact does not refer to the bandwidth of SDRAM. After the frequency and bit width are fixed, the bandwidth cannot be changed. But this is the ideal situation. In the working cycle of the memory, it is impossible to always be in the state of data transmission, because there are necessary processes such as commands and addressing. But the shorter the time taken by these operations, the higher the efficiency of memory work and the better the performance.
The main components of non-data transfer time are various delays and latency. Through the above description, you should clearly see that there are three parameters that are critical to the performance of the memory. They are tRCD, CL, and tRP. Each regular memory module will indicate these three parameter values on the label, showing their sensitivity to performance.
Take the main operation of memory-reading as an example. tRCD determines the interval between row addressing (valid) to column addressing (read/write commands), CL determines the time it takes for the column addressing to data to be actually read, and tRP determines the same L-Bank The speed of conversion of different working lines in Now you can imagine several situations that may be encountered when reading (the CL need not be considered when analyzing the write operation):
1. The line to be addressed and the L-Bank are free. In other words, all the lines of the L-Bank are closed. At this time, the line valid command can be sent directly. The total time before reading the data is tRCD+CL. In this case, we call it page hit (PH, Page Hit ).
2. The row to be addressed happens to be the working row of the previous operation, that is to say, the row to be addressed is already in the strobe valid state. At this time, the column addressing command can be sent directly. The total time before reading the data is only CL This is the so-called back-to-back (Back to Back) addressing, which we call page fast hit (PFH, Page Fast Hit) or page direct hit (PDH, Page Direct Hit).
3. There is already a bank in the L-Bank where the row to be addressed is active (not closed). This phenomenon is called addressing conflict. At this time, it is necessary to perform pre-charging to close the working bank. The line sends a line valid command. As a result, the total elapsed time is tRP+tRCD+CL, which we call the page miss (PM, Page Miss).
Obviously, PFH is the most ideal addressing situation, and PM is the worst addressing situation. The probability of the above three situations is referred to as PHR-PH Rate, PFHR-PFH Rate, PMR-PM Rate. Therefore, system designers (including memory and Northbridge chips) try to improve PHR and PFHR, while reducing PMR, in order to achieve the purpose of improving memory efficiency.
Obviously, this has a direct relationship with the pre-charge management strategy, and there are currently two methods to maximize the PHR. Automatic pre-charging technology is one of them. It automatically pre-charges after each row operation, thereby reducing the possibility of conflicts when addressing different rows of the same L-Bank in the future. However, if you want to open another line of work in the same L-Bank immediately after the current line of work is completed, there is still a tRP delay. How to do? At this time, L-Bank staggered pre-charging is required.
VIA's 4-way interleaved memory control is to pre-charge the next L-Bank to work when one L-Bank is working. In this way, pre-charging and data transmission are interleaved. When the next L-Bank is accessed, tRP has passed and you can directly enter the row valid state. At present, VIA claims that it can interleave 16-way memory across P-Banks and use LRU algorithm for precharge management.
The specific implementation of L-Bank interleaved precharge (access) has been introduced in detail in the second issue of this journal in 2001, and will not be repeated here.
L-Bank interleaved auto-precharge/read timing diagram (click to enlarge): L-Bank 0 and L-Bank 3 implement interleaved reading without intervals, avoiding the impact of tRP on performance.
Neither automatic pre-charging nor interleaved methods can eliminate the delay caused by tRCD. To solve this problem, it is necessary to allow a work line to receive as many work commands as possible before precharging, so as to achieve the effect of back-to-back. At this time, only the read delay caused by CL is left (write Without delay).
How to do this? This is the responsibility of the Northbridge chip. In the above timing diagram, there is a parameter tRAS (Active to Precharge Command, line valid to precharge command interval period). It has a range. For the PC133 standard, the precharge command is generally issued at least 5 clock cycles after the line valid command. The longest interval depends on the chip (basically around 120000ns), otherwise the data of the working line will be lost Danger. Then this means that a working line starts from valid (strobe) and can have a continuous working time of 120,000 ns without precharging. Obviously, as long as the Northbridge chip does not issue a pre-charge (including allowing automatic pre-charge) command, the state of the row will remain open. During this period, there will be no tRCD delay for any read and write operations on the line. It can be seen that the more rows (pages) the Northbridge chip can open at the same time, the larger the PFHR. It should be emphasized that simultaneous opening here does not mean addressing multiple rows at the same time (that is impossible), but means that multiple rows are in the strobe state at the same time. We can see that some SDRAM chipset data will indicate how many pages can be opened at the same time, which can be said to be an important factor in determining its memory performance.
Information on the Intel 845 chipset MCH: which shows that it can support 24 pages open at the same time
However, the number of pages that can be opened simultaneously is also limited. From the addressing principle of SDRAM, it is impossible to have two open rows in the same L-Bank (S-AMP can only serve one row), which limits the total number of pages that can be opened at the same time. Take SDRAM has 4 L-Banks, and Northbridge supports up to 8 P-Banks as an example. In theory, there can only be at most 32 pages that can be open at the same time. And if there is only one P-Bank, then there are only 4 pages left, because only a few L-Banks can open several rows at the same time without interfering with each other. Although the MHC of Intel 845 can support 24 open pages, it also refers to the case of 6 P-Banks (845MCH only supports 6 P-Banks). It can be seen that 845 has brought the number of simultaneous open pages to the extreme.
However, the increased number of open pages at the same time also puts forward certain requirements on the access strategy. In theory, it is necessary to use as many open pages as possible to ensure the shortest delay period. Only when the data does not exist (when reading) or the page is full (when writing), then consider opening a new specified page, which is Continuous read/write with change of direction. When opening a new page, you must close an open page. If the page opened at this time is already the maximum supported by the North Bridge but is not within the theoretical limit, you need a replacement strategy, generally using the LRU algorithm. This is similar to VIA's interleaved control.
DDR-266: DDR-SDRAM memory chip runs at 133MHz
DDR-333: DDR-SDRAM memory chip runs at 166MHz
DDR-400: DDR-SDRAM memory chip runs at 200MHz (the highest DDR specification set by JEDEC)
DDR-500: DDR-SDRAM memory chip runs at 250MHz (non-JEDEC DDR specification)
DDR-600: DDR-SDRAM memory chip runs at 300MHz (non-JEDEC DDR specification)
DDR-700: DDR-SDRAM memory chip runs at 350MHz (non-JEDEC DDR specification)
PC-1600 memory module refers to a DDR-200 memory chip operating at 100MHz, which has a bandwidth of 1.600GB/s
PC-2100 memory module refers to a DDR-266 memory chip operating at 133MHz, which has a bandwidth of 2.133GB/s
PC-2700 memory module refers to a DDR-333 memory chip operating at 166MHz, which has a bandwidth of 2.667GB/s
PC-3200 memory module refers to a DDR-400 memory chip operating at 200MHz, which has a bandwidth of 3.200GB/s
Using the following formula, you can calculate the DDR SDRAM clock.
DDR I/II memory operation clock: actual clock*2. (Due to the simultaneous transmission of data on both sides, the clock of the 200MHz memory will operate at 400MHz.)
Memory bandwidth = memory speed * memory bit width
Standard formula: memory frequency division factor = clock/200→*speed algorithm: external frequency* (frequency division/sync frequency) (using this formula will result in a 4% error)
(1) Bank block address-positioning logic block
(2) Row address and column address --- positioning storage unit
SDRAM focuses on the following signals when reading and writing data:
(1) CLK: clock signal, which is the input signal. The logic state of all input signals of SDRAM needs to be determined by sampling on the rising edge of CLK.
(2) CKE: clock enable signal, which is an input signal, high level is effective. There are two uses of the CKE signal: 1. Turn off the clock to enter the power saving mode; 2. Enter the self-refresh state. When CKE is invalid, all input-related function modules in SDRAM stop working.
(3) CS#: Chip selection signal, which is an input signal, and the low level is effective. Only when the chip select signal is valid, SDRAM can recognize the command sent by the controller. Pay attention to the pull-up when designing.
(4) RAS#: row address strobe signal, which is an input signal, and the low level is effective.
(5) CAS#: column address strobe signal, which is an input signal, and the low level is effective.
(6) WE#: Write enable signal, which is an input signal, low level is effective.
Of course, it also includes the bank[...] address signal, which needs to be determined according to different models. It is also an input signal; the address signal A[...] is an input signal; the data signal DQ[...] is an input/output bidirectional signal; data The mask signal DQM is a bidirectional signal for input and output. The direction is the same as the data flow direction, and the high level is effective. When it is valid, the corresponding data byte appearing on the data bus is shielded by the receiving end.
DDR3 memory. It belongs to the memory product of the SDRAM family, provides higher operating performance and lower voltage than DDR2 SDRAM, and is the successor of DDR2 SDRAM (four times the data rate synchronous dynamic random access memory) (increased to eight times) It is also a popular memory product.
DDR3 SDRAM uses the I/O interface of SSTL 15 for more power saving and faster transmission efficiency. The operating I/O voltage is 1.5V. It is packaged in CSP and FBGA packages, in addition to continuing the ODT, OCD, and Posted CAS of DDR2 SDRAM. In addition to the AL control mode, more advanced CWD, Reset, ZQ, SRT, and PASR functions have been added.
CWD is used for write delay. Reset provides commands for super power saving function, which can stop the operation of DDR3 SDRAM memory particle circuit and enter super power saving standby mode. ZQ is a new terminal resistance calibration function. This line pin provides ODCE (On Die Calibration Engline) to calibrate ODT (On Die Termination) internal interrupt resistance, and new SRT (Self-Reflash Temperature) programmable temperature control memory clock function is added. The addition of SRT allows The memory particles are optimized for temperature, clock and power management. It can be said that the power management function is done in the memory, and the stability of the memory particles is also greatly improved to ensure that the memory particles are not too high. It caused a burnout situation. At the same time, DDR3 SDRAM also added the PASR (Partial Array Self-Refresh) partial bank refresh function, which can be said to do more effective data reading and writing for the entire memory bank to achieve power saving.
The reason why SDRAM becomes DRAM is that it must keep refreshing (Refresh) to retain data, because refreshing (Refresh) is the most important operation of DRAM. So how often should the refresh be repeated, the currently accepted standard is that the upper limit of the effective storage period of the data in the capacitor is 64ms (milliseconds, 1/1000 second), which means that the refresh cycle of each row is 64ms. This refresh rate is: 64ms/line number. When we look at the memory specifications, we often see the logo of 4096 Refresh Cycles/64ms or 8192 Refresh Cycles/64ms, where 4096 and 8192 represent the number of rows in each bank in this chip. The refresh command is valid for one line at a time, and the transmission interval also changes with the total number of lines. It is 15.625 μs (microseconds, 1/1000 milliseconds) at 4096 lines and 7.8125 μs at 8192 lines. HY57V561620 is 8192 refresh cycles / 64ms.
SDRAM is a multi-bank structure. For example, in a SDRAM module with two banks, one bank can be read immediately while the other bank is being pre-charged, so that after one read, it goes immediately When reading the data of the pre-charged bank, you can read it directly without waiting, which greatly improves the access speed of the memory.
In order to realize this function, SDRAM needs to increase the management of multiple banks and realize the pre-charge control of the banks. In an SDRAM with more than two banks, there is usually one more pin called BAn, which is used to select between multiple banks.
SDRAM has multiple working modes, and the internal operation is a complicated state machine. The pins of SDRAM devices are divided into the following categories.
(1) Control signals: including chip select, clock, clock enable, row and column address selection, read and write valid, and data valid.
(2) Address signal: time-division multiplexing pin, select the pin according to the row and column address, and control the input address as row address or column address. .
(3) Data signal: bidirectional pin, effectively controlled by data.
All operations of SDRAM are synchronized with the clock. Various input commands can be generated according to the state of the clock rising edge control pin and address input.
Mode register setting command.
Activate the command.
Read command with precharge.
Write command with precharge.
Automatic refresh command.
Self refresh command.
Sudden stop command.
No operation command.
According to the input command, the SDRAM state transitions between internal states. The internal state includes the mode register setting state, activation state, precharge state, write state, read state, precharge read state, precharge write state, auto refresh state and self refresh state.
The operation commands supported by SDRAM include initial configuration, precharge, row activation, read operation, write operation, automatic refresh, and self-refresh. All operation commands are input through the control lines CS#, RAS#, CAS#, WE# and the address line and body selection address BA.
1. Line activation
The row activation command selects any row of the memory bank in the idle state to make it enter the read/write ready state. The number of clock ticks from the time the body is activated to allowing input of read/write commands depends on the internal characteristic delay and clock frequency. There are 4 individuals in HY57V561620. In order to reduce the number of device gates, some circuits between the 4 individuals are common, so they cannot be activated at the same time, and the transition from the activation of one body to the activation of another body must also be guaranteed for a certain time. interval.
The pre-charge command is used to pre-charge the activated row to end the active state. The precharge command can be applied to a single body, or to all bodies at the same time (through all body precharge commands). For burst write operations, you must ensure that the write operation is completed before writing the precharge command, and use DQM to prohibit the continued writing of data. After the precharge is completed, it returns to the idle state and can be activated again. At this time, operation commands such as low power consumption, automatic refresh, self-refresh, and mode setting can also be input.
The rewriting operation in the precharge is the same as the refresh operation, except that the precharge is not periodic, but only performed after the read operation. Because the read operation will destroy the charge in the memory. Therefore, the memory is not only refreshed every 64ms, but also refreshed after each read operation.
3. Automatic pre-charging
If the A10/AP bit is set to "1" in a burst read or burst write command, a precharge action is automatically added after the read and write operation is completed. The operation line ends the active state, but no new operation commands can be sent to the device until the internal state machine returns to the idle state.
4. Burst reading
The burst read command allows several lines of data to be read out continuously after a row in a volume is activated. The first data is presented on the data line after the specified CAS delay beat, and a new data will be read for each clock beat in the future. The burst read operation can be aborted by a new burst read/write command of the same body or a different body or a precharge command and a burst stop command of the same body.
5. Burst write
The burst write command is similar to the burst read command, allowing a row in a volume to be activated to write several data in succession. The first write data and the burst write command are given on the data line at the same time, and then each clock tick gives a new data. The input buffer stops accepting data after the burst data amount meets the requirements. The burst write operation can be aborted by the burst read/write command or DQM data input mask command and precharge command or burst stop command.
6. Automatic refresh
Due to the leakage phenomenon of the dynamic memory storage unit, in order to maintain the correctness of the data of each storage unit, HY57V561620 must ensure that all storage units are refreshed within 64ms. An automatic refresh cycle can only refresh one row of the storage unit, and the internal refresh address counter automatically increases by "1" after each refresh operation. Only when all the bodies are idle (because the corresponding rows of 4 individuals are refreshed at the same time) and are not in low power mode, the automatic refresh operation can be started. During the refresh operation, only empty operations can be entered. After the refresh operation is completed, all the bodies are idle. status. The device can execute an auto-refresh command every 7.8 μs, or it can refresh all cells in a certain period of time within 64 ms.
Self-refresh is another refresh method of dynamic memory, which is usually used to keep SDRAM data in low power consumption mode. In self-refresh mode, SDRAM prohibits all internal clocks and input buffers (except CKE). In order to reduce power consumption, the refresh address and refresh time are all generated internally by the device. Once the self-refresh mode is entered, it can only be activated by turning CKE low, and any other input will have no effect. After giving the command to exit the self-refresh mode, a certain amount of no-operation input must be kept to ensure that the device completes the exit from the self-refresh mode. If the centralized automatic refresh method is used during normal work, a centralized automatic refresh operation (for HY57V561620, 8192) must be performed after exiting the self-refresh mode.
8. Clock and clock shield
The clock signal is a synchronous signal for all operations, and the rising edge is valid. The clock mask signal CKE determines whether to apply the clock input to the internal circuit. During read and write operations, the next beat after CKE goes low freezes the output state and burst address until CKE goes high. When all the bodies are idle, the next tick SDRAM after CKE goes low enters a low-power mode and remains until CKE goes high.
9. DQM operation
DQM is used to shield the input and output operations. For the output, it is equivalent to the door open signal. For the input, the data on the bus is prohibited from being written into the storage unit. The DQM delays 2 clock cycles for read operations to take effect, while for write operations it is effective when the beat is taken.
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