PQFP (Plastic Quad Flat Package) is a form of chip packaging. PQFP packaged chips have pins on all sides, and the total number of pins is generally more than 100, and the distance between the pins is very small, and the pins are also very thin. Generally, large-scale or ultra-large-scale integrated circuits use this type of packaging. Chips packaged in this form must use SMT (Surface Mount Technology) to solder the pins on the side of the chip to the motherboard. Chips installed by SMT do not need to punch holes on the motherboard, and generally there are solder joints with corresponding pins designed on the surface of the motherboard. Align the pins of the chip with the corresponding solder joints, and the soldering to the motherboard can be realized.
PQFP package is suitable for SMT surface mounting technology to install wiring on PCB, suitable for high frequency use, it has the advantages of easy operation, high reliability, mature process, low price and so on.
However, the shortcomings of PQFP packaging are also obvious. Due to the limited side length of the chip, the number of pins in the PQFP packaging method cannot be increased, which limits the development of graphics acceleration chips. Parallel pins are also a stumbling block that hinders the continued development of PQFP packaging. Because parallel pins will generate a certain capacitance when transmitting high-frequency signals, which will generate high-frequency noise signals. In addition, long pins can easily absorb this interference noise. Like the antenna of a radio, hundreds of "antennas" interfere with each other, making it difficult for PQFP-packaged chips to work at higher frequencies. In addition, the chip area/package area ratio of the PQFP package is too small, which also limits the development of the PQFP package. In the late 1990s, as BGA technology continued to mature, PQFP was finally eliminated by the market.
The PQFP package has connections only on the periphery of the package. To increase the number of pins, the pitch was reduced from 50 mils (one thousandth of an inch) (found on small form factor packages) to 20 and the last 12 mils (1.27 mm, 0.51 mm, and 0.30 mm, respectively). However, this tight lead spacing makes soldering bridges more likely to occur, and places higher demands on the soldering process and component alignment during assembly. The rear pin grid array (PGA) and ball grid array (BGA) packages allow connections on the package area, not just around the edges, allowing higher pin counts and similar package sizes, and reducing problems with Close lead spacing.
The basic shape is a flat rectangular (usually square) body with leads on all four sides, but the design has many variations. These usually differ only in the number of leads, pitch, size and materials used (usually used to improve thermal characteristics). The obvious change is the Bumpered Quad Flat Package (BQFP), which has extensions at the four corners to protect the leads from mechanical damage before soldering the unit.
Heat sink quad flat package, heat sink ultra-thin quad flat no-lead (HVQFN) is a package that does not have component leads extending from the IC. The pads are spaced along the sides of the IC and have exposed die that can be used as grounds. The spacing between the pins can vary.
TQFP offers the same advantages as metric QFP, but thinner. The thickness of a conventional QFP is 2.0 to 3.8 mm, depending on the size. The TQFP package includes 32 leads with a lead pitch of 0.8 mm, a package size of 5 mm×5 mm×1 mm, 256 leads, a 28 mm square, 1.4 mm thick, and a lead pitch of 0.4 mm.
TQFP helps to solve problems such as increasing circuit board density, chip shrinking procedures, streamlining the final product configuration and portability. The number of leads ranges from 32 to 176. The body size ranges from 5 mm x 5 mm to 20 x 20 mm. Copper lead frames are used for TQFP. The lead pitches available for TQFP are 0.4 mm, 0.5 mm, 0.65 mm, 0.8 mm and 1.0 mm. PQFP or plastic quad flat pack is a type of QFP, as is the thinner TQFP package. The thickness of the PQFP package can vary from 2.0 mm to 3.8 mm. A thin quad flat pack (LQFP) is a surface mount integrated circuit package format in which component leads extend from each of the four sides. The pins are numbered counterclockwise from the index point. The spacing between the pins can be varied; common spacings are 0.4, 0.5, 0.65 and 0.80 mm intervals.
There are two types of ceramic QFP packages, CERQUAD and CQFP:
CERQUAD:
Therefore, the lead frame is connected between the two ceramic layers of the package. The lead frame uses glass connections. This software package is a variant of the CERDIP software package. CERQUAD packaging is a "low cost" alternative to CQFP packaging and is mainly used for ground applications. The main ceramic package manufacturers are Kyocera, NTK, . and provide a complete range of pincount
CQFP:
Therefore, the leads are soldered on top of the package. The package is a multi-layer package that provides HTCC (High Temperature Co-fired Ceramic). The number of adhesive layers can be one, two or three. The package uses a thickened nickel layer, except for wire bonding and decoupling capacitor welding on the top of the package. These packages are sealed. Two methods are used for hermetic sealing: eutectic gold-tin alloy (melting point 280°C) or seam welding. Seam welding significantly reduces the temperature rise inside the package (eg, die connection). This package is the main package for the Space project. Due to the large size of the CQFP package, parasitic effects are very important for the package. Power supply decoupling is improved by installing decoupling capacitors on top of the package. For example, TI provides a 256-pin CQFP package, where the decoupling capacitor can be soldered on top of the package [5], for example, a test expert 256-pin CQFP package, where the decoupling capacitor can be soldered on the top of the package [6] The main ceramic package manufacturer is Kyocera (Japan), NTK (Japan), testing experts (Russia), etc., and provide a complete range of pincount. The maximum number of pins is 352 pins.
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 100-Pin VTQFP
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 44-Pin VQFP
FPGA Virtex Family 236.666K Gates 5292 Cells 333MHz 0.22um Technology 2.5V 352-Pin Metal BGA
FPGA Virtex Family 236.666K Gates 5292 Cells 333MHz 0.22um Technology 2.5V 240-Pin PQFP
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 256-Pin BGA
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