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PMOS refers to an n-type substrate, a p-channel, and a MOS tube that carries current by the flow of holes. Full name: Positive channel Metal Oxide Semiconductor; Alias: positive MOS.


Basic Information

PMOS refers to n-type substrate, p-channel, MOS tube that transports current by the flow of holes

Full name: positive channel Metal Oxide Semiconductor

Aliases: positive MOS

Metal oxide semiconductor field effect (MOS) transistors can be divided into two categories: N-channel and P-channel. P-channel silicon MOS field-effect transistors have two P+ regions on the N-type silicon substrate, called source and The drain is not conductive between the two electrodes. When a sufficient positive voltage is applied to the source (the gate is grounded), the surface of the N-type silicon under the gate presents a P-type inversion layer, which becomes the channel connecting the source and the drain . Changing the gate voltage can change the density of holes in the channel, thereby changing the resistance of the channel. This MOS field effect transistor is called a P-channel enhancement type field effect transistor. If the channel of the P-type inversion layer already exists on the surface of the N-type silicon substrate without applying the gate voltage, adding the appropriate bias voltage can increase or decrease the resistance of the channel. Such a MOS field effect transistor is called a P-channel depletion field effect transistor. Collectively referred to as PMOS transistors.

The hole mobility of the P-channel MOS transistor is low, so the transconductance of the PMOS transistor is smaller than that of the N-channel MOS transistor when the geometrical size of the MOS transistor and the absolute value of the operating voltage are equal. In addition, the absolute value of the threshold voltage of the P-channel MOS transistor is generally high, requiring a higher operating voltage. The voltage magnitude and polarity of its power supply are incompatible with bipolar transistors-transistor logic circuits. Due to the large logic swing, long charge and discharge process, and the small transconductance of the device, PMOS has a lower operating speed. After the appearance of NMOS circuits (see N-channel metal-oxide-semiconductor integrated circuits), most of them have been used by NMOS circuits. replace. However, due to the simple process and low price of PMOS circuits, some medium- and small-scale digital control circuits still use PMOS circuit technology.

The MOSFET has three pins, generally G, D, and S. When the control signal is added between G and S, the conduction and cutoff between D and S can be changed. PMOS and NMOS are completely similar in structure, the difference is the doping type of substrate and source and drain. To put it simply, NMOS is formed on a P-type silicon substrate by selective doping to form an N-type doped region as the source and drain regions of NMOS; PMOS is formed on a N-type silicon substrate by selective doping The P-type doped region serves as the source and drain regions of the PMOS. The distance between the two source-drain doped regions is called the channel length L, and the effective source-drain region size perpendicular to the channel length is called the channel width W. For this simple structure, the source and drain of the device are completely symmetrical. Only in the application can the specific source and drain be finally confirmed according to the source and drain current flow direction.

The working principle of PMOS is similar to NMOS. Because PMOS is an N-type silicon substrate, most of the carriers are electrons, minority carriers are holes, and the doping type of the source and drain regions is P type. Therefore, the operating condition of PMOS is relative to the source on the gate Negative voltage is applied to the pole, that is, negatively charged electrons are applied to the gate of the PMOS, and the movable positive charge holes and the depletion layer with a fixed positive charge are induced on the substrate, regardless of the presence of silicon dioxide Under the influence of the charge, the amount of positive charge induced in the substrate is equal to the amount of negative charge on the PMOS gate. When a strong inversion is reached, under the effect of a negative drain-source voltage relative to the source, the positive charge holes at the source reach the drain through the conducting P-channel, forming a source-drain current from source to drain. Similarly, the more negative the VGS (the greater the absolute value), the smaller the on-resistance of the channel and the larger the current value.

Like the NMOS, the working area of the turned-on PMOS is also divided into an unsaturated zone, a critical saturation point and a saturated zone. Of course, regardless of whether NMOS or PMOS, when the inversion channel is not formed, it is in the cut-off region, and its voltage condition is:



It is worth noting that both VGS and VTP of PMOS are negative.

PMOS integrated circuit is a device suitable for application in the field of low speed and low frequency. PMOS integrated circuits are powered by -24V.

MOS field-effect transistors have a high input impedance, which facilitates direct coupling in the circuit, making it easy to make large-scale integrated circuits.

Comparison of various FET characteristics

At the International Electronic Device Conference (IEDM) in December 2004, it was stated that the dual stress liner (DSL) method resulted in 15% and 32% increase in effective drive current in NMOS and PMOS, respectively, and 11% and 20% increase in saturation drive current, respectively. %. The hole mobility of PMOS can be increased by 60% without using SiGe, which has become the focus of other strained silicon research.

Application in reverse protection circuit

PMOS is used in the reverse protection circuit, and the use of diodes is not required. The voltage drop is smaller and the dissipation is less. Don't look at a parasitic forward diode, but it is completely useless. When the circuit is normally energized, GATE is connected to the zero potential far below the D terminal, and this PMOS is completely turned on. When the power is reversed, the GATE potential is much higher than the S terminal, and the PMOS is completely cut off.


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