OLMC

Structure type

The four multiplexers in OLMC are output data selector OMUX, product term data selector PTMUX, tri-state data selector TSMUX and feedback data selector FMUX, which are in the control signal AC (0) and AC1 (n) Under the effect of, can achieve different output circuit structure.

As can be seen from the structure of the above OLMC, OLMC can be reconfigured under the control of SYN, AC(0), AC1(n), that is, it can work in five different modes: dedicated input mode; dedicated combined output mode; with feedback Combined output mode; sequential output combined mode; register output mode. SYN is 0 or 1 to determine the configured OLMC is a sequential or combinational logic circuit, AC (0), AC1 (n) is used to control the circuit structure of OLMC, AC (0) is shared by the used OLMC, and AC1 ( n) is unique for each OLMC.

1) When SYN=1, AC(0)=0, and AC1(n)=1, the circuit structure of OLMC(n) is a dedicated input mode, which is a combinational logic circuit. At this time, pins 1 and 11 can be used as ordinary data input terminals, the output tri-state buffer is disabled, so that the corresponding I/O terminal cannot be used as an output and can only be used as an input terminal, and the input signal needs to pass through the adjacent stage OLMC's FMUX feedback back to the AND logic array input. It should be noted that from the structure diagram of GAL16V8, it can be seen that OLMC (15) and OLMC (16) are not connected to FMUX, so they cannot be used as a dedicated input mode, that is, 101 mode.

2) When SYN=1, AC(0)=0, and AC1(n)=0, the circuit structure of OLMC(n) is a dedicated combined output mode, which is a combined logic circuit. At this time, pins 1 and 11 can be used as ordinary data input terminals, the output tri-state buffer is in working state, the output is always allowed, and the output of the XOR gate is sent to the tri-state buffer through OMUX. Because the tri-state buffer is an inverter, the combined logic function output when XOR(n)=0 is active low, and active when XOR(n)=1. When AC1 (m) of the adjacent OLMC is also 0, FMUX is grounded and there is no feedback signal. The corresponding I/O terminal can only be used as a pure combination output and cannot be used as a feedback input.

3) When SYN=1, AC(0)=1, and AC1(n)=1, the circuit structure of OLMC(n) is a combined output mode with feedback. Pins 1 and 11 can be used as ordinary data input terminals. The output tri-state buffer is controlled by the first product term, and the output signal of the tri-state buffer is fed back to the input of the AND logic array. In 111 mode, as long as one OLMC works in 111 mode, all 8 OLMCs must work in 111 mode; OLMC (19) and OLMC (12) shown in Figure 8.19 are used to maintain the JEDEC fuse graph with the PAL device. It is fully compatible with AC (0) and SYN instead of AC1 (n), so the output of OLMC (19) and OLMC (12) cannot be fed back to "AND logic array". ?

4) When SYN=0, AC(0)=1, and AC1(n)=0, the circuit structure of OLMC(n) is the register output mode, which is a sequential logic circuit. Pin 1 is the input terminal of the clock signal CK, and pin 11 is the input terminal of the common tri-state control signal; the output of the XOR gate is sent to the D flip-flop for registration, and the Q terminal output of the D flip-flop is sent to the tri-state output buffer. At the same time, the FMUX feedbacks the input to the AND logic array. The three-state input buffer is controlled by the 11-pin external signal. All (8) can work in the 010 mode input by this register.

5) When SYN=0, AC(0)=1, and AC1(n)=1, the circuit structure of OLMC(n) is the combined output mode of sequential logic. At this time, the output of the XOR gate is directly sent to the output tri-state buffer, the output tri-state buffer is controlled by the first product term, and the I/O (n) signal is fed back to the AND logic array via FMUX. It should be noted that the OLMC working in the 011 mode cannot exist alone, and must coexist with the 010 mode OLMC output by the register in a GAL chip, that is, the OLMC working in the 011 mode is a combinational logic part in the sequential logic circuit At this time, pin 1 is still the input terminal of the clock signal CK, and pin 11 is also the input terminal of the common three-state control signal, but CK and are used by other OLMCs working in 010 mode.

OLMC is shrot for output logic macrocell It is a key components of PLD As is shown in the logic schematic diagram, the OR gate has 8 inputs from AND array. The XOR bit of each macrocell controls the polarity of the output, while the AC1 bit of each of the macrocells controls the input/output configuration.OLMC has four MUX, including OMUX for choosing data, PTMUX which is called produce term MUX, TSMUX for choosing the state of three state output gate, and FMUX. The FMUX is controlled by AC(0) and AC(n). Programming some bits(syn, AC(0), AC(n), etc.) leads to various combinations of configuration of OLMC via 4 MUX.