NMOS is called N-Metal-Oxide-Semiconductor in English. It means N-type metal-oxide-semiconductor, and the transistor with this structure is called NMOS transistor. MOS transistors are divided into P-type MOS transistors and N-type MOS transistors. The integrated circuit composed of MOS tubes is called MOS integrated circuit, the circuit composed of NMOS is NMOS integrated circuit, the circuit composed of PMOS tube is PMOS integrated circuit, the complementary MOS circuit composed of NMOS and PMOS two tubes, namely CMOS circuit .
NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor).
On a P-type silicon substrate with a low doping concentration (providing a large number of movable holes), two N+ regions with high doping concentration are produced (the N+ region has a large number of electron sources that provide free electrons for current flow), And lead two electrodes with aluminum metal, as drain D and source S respectively. Then the semiconductor surface is covered with a thin insulating layer of silicon dioxide (SiO2), and an aluminum electrode (usually polysilicon) is installed on the insulating layer between the drain and the source as the gate G. An electrode B is also drawn on the substrate, which constitutes an N-channel enhancement type MOS tube. The source and substrate of the MOS tube are usually connected together (most of the tubes are connected before leaving the factory).
The control effect of vGS on iD and channel
① When vGS=0
As can be seen from Figure 1(a), there are two back-to-back PN junctions between the drain d and source s of the enhanced MOS tube. When the gate-source voltage vGS=0, even if the drain-source voltage vDS is added, and regardless of the polarity of vDS, there is always a PN junction in the reverse bias state, and there is no conductive channel between the drain-source, So the drain current iD≈0 at this time.
② vGS>0
If vGS>0, an electric field is generated in the SiO2 insulating layer between the gate and the substrate. The direction of the electric field is perpendicular to the electric field of the semiconductor surface from the gate to the substrate. This electric field can repel holes and attract electrons.
Reject holes: The holes in the P-type substrate near the gate are repelled, leaving unacceptable acceptor ions (negative ions) to form a depletion layer. Attract electrons: attract electrons (minority) in the P-type substrate to the substrate surface.
Formation of conductive channels
When the vGS value is small and the ability to attract electrons is not strong, there is still no conductive channel between the drain and the source, as shown in Figure 1(b). As vGS increases, the electrons attracted to the surface layer of the P substrate increase. When vGS reaches a certain value, these electrons form an N-type thin layer on the surface of the P substrate near the gate and are connected to the two N+ regions. Through, a N-type conductive channel is formed between the drain and the source, and its conductivity type is opposite to that of the P substrate, so it is also called an inversion layer, as shown in FIG. 1(c). The larger the vGS, the stronger the electric field acting on the semiconductor surface, the more electrons attracted to the P substrate surface, the thicker the conductive channel, and the smaller the channel resistance.
The gate-source voltage at the beginning of the channel formation is called the turn-on voltage, which is expressed by VT.
The N-channel MOS tube cannot form a conductive channel when vGS<VT, and the tube is in the off state. Only when vGS≥VT, there is a channel formation. This kind of MOS tube that can form a conductive channel only when vGS≥VT is called an enhanced MOS tube. After the channel is formed, a drain current is generated by adding a forward voltage vDS between the drain and the source.
The impact of vDS on iD
When vGS>VT is a certain value, the effect of the drain-source voltage vDS on the conductive channel and current iD is similar to the junction field effect transistor.
The voltage drop generated by the drain current iD along the channel makes the voltage between each point in the channel and the gate no longer equal, the voltage near the source is the largest, where the channel is the thickest, and the voltage at the drain is the smallest, its value is VGD=vGS-vDS, so here the channel is the thinnest. However, when vDS is small (vDS<vGS–VT), it has little effect on the channel. At this time, as long as vGS is constant, the channel resistance is almost constant, so iD changes approximately linearly with vDS.
With the increase of vDS, the channel near the drain becomes thinner and thinner. When vDS is increased to make VGD=vGS-vDS=VT (or vDS=vGS-VT), the channel appears pre-pinched off at the end of the drain , As shown in Figure 2(b). Continue to increase vDS, the pinch breakpoint will move toward the source, as shown in Figure 2(c). Since almost all the increased part of vDS falls in the pinch-off region, iD hardly increases with the increase of vDS. The tube enters the saturation region, and iD is almost determined by vGS.
PMOS is used in the reverse protection circuit, and the use of diodes is not required. The voltage drop is smaller and the dissipation is less. Don't look at a parasitic forward diode, but it is completely useless. When the circuit is normally energized, GATE is connected to the zero potential far below the D terminal, and this PMOS is completely turned on. When the power is reversed, the GATE potential is much higher than the S terminal, and the PMOS is completely cut off.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 676-Pin FBGA
FPGA Virtex-II Family 1.5M Gates 17280 Cells 750MHz 0.15um Technology 1.5V 896-Pin FCBGA
FPGA Virtex-II Family 1.5M Gates 17280 Cells 820MHz 0.15um Technology 1.5V 575-Pin BGA
FPGA XC3000 Family 4.5K Gates 224 Cells 100MHz 5V 132-Pin PPGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 48-Pin QFN EP
Support
