Metal-oxide semiconductor field effect transistor, referred to as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect ransistor that can be widely used in analog circuits and digital circuits ). MOSFETs can be divided into two types of "N-type" and "P-type" according to their "channel" (working carrier) polarity. They are also commonly referred to as NMOSFET and PMOSFET. Other abbreviations include NMOS, PMOS, etc. .
FIG. 1 is a cross-sectional view of a typical planar N-channel enhancement type NMOSFET. It uses a piece of P-type silicon semiconductor material as a substrate, diffuses two N-type regions on its surface, then covers it with a layer of silicon dioxide (SiO2) insulating layer, and finally makes it by etching above the N region Two holes are made into three electrodes on the insulating layer and the two holes by metallization: G (gate), S (source) and D (drain).
It can be seen from FIG. 1 that the gate G is insulated from the drain D and the source S, and there are two PN junctions between D and S. In general, the substrate and the source are connected together internally, which is equivalent to a PN junction between D and S.
In order to improve the characteristics of certain parameters, such as increasing the operating current, increasing the operating voltage, reducing the on-resistance, and improving the switching characteristics, there are different structures and processes, which constitute the so-called VMOS, DMOS, TMOS and other structures. Although they have different structures, their working principles are the same, so we will not introduce them one by one here.
To make the enhanced N-channel MOSFET work, a positive voltage VGS is added between G and S and a positive voltage VDS is added between D and S, and a forward operating current ID is generated. The operating current ID can be controlled by changing the voltage of VGS.
If VGS is not connected first (that is, VGS=0), a positive voltage VDS is applied between the D and S poles, and the PN junction between the drain D and the substrate is reversed, so the drain source cannot conduct electricity. If a voltage VGS is applied between the gate G and the source S. At this time, the gate and the substrate can be regarded as the two plates of the capacitor, and the oxide insulating layer serves as the dielectric of the capacitor. When VGS is added, positive charges are induced at the interface between the insulating layer and the gate, and negative charges are induced at the interface between the insulating layer and the P-type substrate. The negative charge induced in this layer is opposite to the polarity of the majority carriers (holes) in the P-type substrate, so it is called the "inversion layer". This inversion layer may connect the drain and the source to the two N-type regions. Connected together to form a conductive channel. When the VGS voltage is too low, less negative charge is induced, and it will be neutralized by the holes in the P-type substrate, so in this case, there is still no current ID between the drain and the source. When VGS increases to a certain value, its induced negative charge communicates the two separated N regions to form an N channel. This critical voltage is called the turn-on voltage (or threshold voltage, threshold voltage), which is represented by the symbol VT (generally specified VGS at ID=10uA is regarded as VT). When VGS continues to increase, the negative charge increases, the conductive channel expands, the resistance decreases, and the ID also increases, and has a better linear relationship, as shown in Figure 3. This curve is called the conversion characteristic. Therefore, within a certain range, it can be considered that changing VGS to control the resistance between the drain and the source achieves the function of controlling the ID.
Due to this structure, when VGS=0, ID=0, this MOSFET is called enhancement mode. Another type of MOSFET also has a certain ID (called IDSS) when VGS=0. This type of MOSFET is called a depletion mode. Its structure is shown in Figure 4, and its transfer characteristics are shown in Figure 5. VP is the pinch-off voltage (ID=0).
The main difference between the depletion mode and the enhancement mode is that there are a large number of positive ions in the manufacturing SiO2 insulating layer, which causes more negative charges to be induced at the interface of the P-type substrate, that is, the P-type silicon in the middle of the two N-type regions A thin layer of N-type silicon is formed inside to form a conductive channel, so when VGS=0, there is also a certain ID (IDSS) when VDS is applied; when VGS has a voltage (which can be positive or negative voltage), change the induction The number of negative charges, thus changing the size of the ID. VP is -VGS when ID=0, which is called pinch-off voltage.
Looking at the naming of MOSFET from the surface of the name, in fact, people will get the wrong impression. Because the first letter M representing "metal" in the MOSFET does not exist in most of the current similar components. The gate electrode of the early MOSFET used metal as its material, but with the advancement of semiconductor technology, the gate of the MOSFET used polysilicon instead of metal. In the processor, the polysilicon gate is no longer the mainstream technology. Starting from Intel's 45nm line width P1266 processor, the gate began to use metal.
MOSFET is conceptually an "Insulated-Gate Field Effect Transistor" (IGFET), and the gate insulating layer of IGFET may be an oxide layer used by other substances than MOSFET. Some people prefer to use IGFETs when referring to field effect transistor elements with polysilicon gates, but most of these IGFETs refer to MOSFETs.
MOSFET is conceptually an "Insulated-Gate Field Effect Transistor" (IGFET), and the gate insulating layer of IGFET may be an oxide layer used by other substances than MOSFET. Some people prefer to use IGFETs when referring to field effect transistor elements with polysilicon gates, but most of these IGFETs refer to MOSFETs.
The oxide layer in the MOSFET is located above its channel. Depending on the operating voltage, the thickness of this layer of oxide is only tens to hundreds of angstroms. The material is usually silicon dioxide (SiO2), but some new The advanced process can already use silicon oxynitride (SiON) as the oxide layer.
Today, the material of semiconductor components is usually silicon (silicon) as the first choice, but some semiconductor companies have developed processes using other semiconductor materials, the most famous of which is the silicon-germanium process developed by IBM using a mixture of silicon and germanium ( silicon-germanium process, SiGe process). Unfortunately, many semiconductor materials with good electrical properties, such as gallium arsenide (GaAs), cannot be used to manufacture MOSFET devices because they cannot grow an oxide layer of sufficient quality on the surface.
When a sufficiently large potential difference is applied between the gate and source of the MOSFET, the electric field will form an induced charge on the semiconductor surface below the oxide layer, and the so-called "inversion channel" Will form. The polarity of the channel is the same as its drain and source. Assuming that the drain and source are N-type, then the channel will also be N-type. After the channel is formed, the MOSFET can pass current, and depending on the voltage value applied to the gate, the amount of current that can flow through the channel of the MOSFET will also change under its control.
There are many variations of circuit symbols commonly used in MOSFETs. The most common design is to use a straight line to represent the channel, two lines perpendicular to the channel represent the source and drain, and the left side parallel to the channel and the shorter line represents the gate. As shown below. Sometimes the straight line representing the channel is replaced by a dashed line to distinguish between enhancement mode MOSFET (enhancement mode MOSFET) or depletion mode MOSFET (depletion mode MOSFET). In addition, it is divided into two types of NMOSFET and PMOSFET. The circuit symbol is as shown in the figure Display (the direction of the arrow is different).
Since the MOSFET on the integrated circuit chip is a four-terminal device, in addition to the gate, source, and drain, there is still a base (Bulk or Body). In the MOSFET circuit symbol, the arrow direction extending from the channel to the right indicates that the device is an N-type or P-type MOSFET. The direction of the arrow is always from the P terminal to the N terminal, so the arrow from the channel to the base terminal is a P-type MOSFET, or PMOS for short (the channel of this component is P-type); otherwise if the arrow points from the base to the channel, it represents the base Extremely P-type, and the channel is N-type, this device is N-type MOSFET, referred to as NMOS. In a general distributed MOSFET device (discrete device), the base and source are usually connected together, so the distributed MOSFET is usually a three-terminal device. MOSFETs in integrated circuits usually use the same base (common bulk), so the polarity of the base is not marked, and a circle is added to the gate of the PMOS to show the difference (this is a foreign symbol, see the national standard symbol see Figure).
In this way, there are four types of MOSFETs: P-channel enhancement type, P-channel depletion type, N-channel enhancement type, and N-channel depletion type. Their circuit symbols and application characteristic curves are shown in the figure below.
The core of MOSFET: metal-oxide layer-semiconductor capacitor
The metal-oxide layer-semiconductor structure MOSFET is structured with a metal-oxide layer-semiconductor capacitor as the core (as mentioned above, most MOSFETs today use polysilicon instead of metal as their gate material), and the material of the oxide layer is mostly Silicon dioxide, underneath is silicon as the base, and above it is polysilicon as the gate. This structure is exactly equal to a capacitor. The oxide layer plays the role of dielectric material in the capacitor, and the capacitance value is determined by the thickness of the oxide layer and the dielectric constant of silicon dioxide. The gate polysilicon and the base silicon become the two ends of the MOS capacitor.
When a voltage is applied across the MOS capacitor, the charge distribution of the semiconductor changes accordingly. Consider a MOS capacitor formed by a P-type semiconductor (with a hole concentration of NA). When a positive voltage VGB is applied to the gate and base terminals (see figure), the hole concentration will decrease and the electron concentration will increase. When VGB is strong enough, the electron concentration near the gate terminal will exceed the hole. This region in the P-type semiconductor where the electron concentration (negatively charged) exceeds the hole (positively charged) concentration is the so-called inversion layer.
The characteristics of MOS capacitors determine the operating characteristics of MOSFETs, but a complete MOSFET structure also requires a source that provides a majority carrier and a drain that accepts these majority carriers.
structure
A perspective cross-sectional view of an NMOS transistor The left figure is a cross-sectional view of an N-type MOSFET (hereinafter referred to as NMOS). As mentioned earlier, the core of the MOSFET is the MOS capacitor located in the center, and its source and drain are on the left and right sides. The characteristics of the source and drain must be N-type (ie NMOS) or P-type (ie PMOS). The "N+" marked on the source and drain of the NMOS on the right represents two meanings: (1) N represents the impurity polarity doped in the source and drain regions; N (2) "+" represents this region as A highly doped region (heavily doped region), that is, the electron concentration in this region is much higher than other regions. The source and drain are separated by a region of opposite polarity, also known as the base (or base) region. If it is NMOS, then the doping of its base region is P-type. On the contrary, for PMOS, the substrate should be N-type, while the source and drain are P-type (and heavy (pronounced zhong) doped P+). The doping concentration of the substrate does not need to be as high as the source or drain, so there is no "+" in the figure on the right.
For this NMOS, only the surface area of the semiconductor directly below the MOS capacitor is used as a channel to pass carriers. When a positive voltage is applied to the gate, negatively charged electrons will be attracted to the surface, forming a channel, so that the majority of the N-type semiconductor carrier-electrons can flow from the source to the drain. If this voltage is removed, or a negative voltage is applied, the channel cannot be formed and carriers cannot flow between the source and drain.
Assuming that the operation object is changed to PMOS, then the source and drain are P-type, and the substrate is N-type. When a negative voltage is applied to the gate of the PMOS, the holes on the semiconductor will be attracted to the surface to form a channel, and most of the semiconductor carriers-holes can flow from the source to the drain. Assuming that this negative voltage is removed, or a positive voltage is added, the channel cannot be formed, and the carrier cannot flow between the source and the drain.
In particular, the source in MOSFET means "provide the source of majority carriers". For NMOS, most carriers are electrons; for PMOS, most carriers are holes. In contrast, the drain is the endpoint that accepts the majority carrier.
There are many parameters of the field effect tube, including DC parameters, AC parameters and limit parameters, but in general use, pay attention to the following main parameters:
1. IDSS—saturation drain-source current. It refers to the drain-source current when the gate voltage UGS=0 in the junction or depletion type insulated gate field effect transistor.
2. UP—Clamp off voltage. It refers to the gate voltage of the junction or depletion type insulated gate field effect transistor, which just turns off between the drain and the source.
3. UT—Turn on the voltage. Refers to the gate voltage when the drain-source is just turned on in the enhanced insulated gate field effect tube.
4. gM—transconductance. It represents the gate-source voltage UGS-controlling ability of the drain current ID, that is, the ratio of the change amount of the drain current ID to the change amount of the gate-source voltage UGS. gM is an important parameter to measure the amplification ability of the field effect tube.
5. BUDS—Drain source breakdown voltage. It refers to the maximum drain-source voltage that the field effect tube can withstand when the gate-source voltage UGS is fixed. This is a limit parameter, and the working voltage applied to the FET must be less than BUDS.
6. PDSM—Maximum power dissipation. It is also a limit parameter, which refers to the maximum allowable drain-source power dissipation when the performance of the field effect tube does not deteriorate. When in use, the actual power consumption of the FET should be less than PDSM and leave a certain margin.
7. IDSM—Maximum drain-source current. It is a limit parameter, which refers to the maximum current allowed to pass between the drain and the source when the field effect tube is working normally. The working current of the field effect tube should not exceed IDSM.
There are two naming methods.
FETs usually have the following two naming methods.
The first naming method is to use the "Chinese semiconductor device model nomenclature" part 3, 4 and 5 to name, part 3 of which uses the letter CS to indicate the field effect tube, part 4 uses Arabic numerals to indicate the device serial number , Part 5 uses Chinese Pinyin letters to indicate the specification number. For example, CS2B, CS14A, CS45G, etc.
The second naming method is the same as the bipolar transistor. The first digit uses numbers to represent the number of electrodes; the second digit uses letters to represent the polarity (where D is N channel and C is P channel); the third digit uses letters to represent Type (where J stands for junction field effect transistor and O stands for insulated gate field effect transistor). For example, 3DJ6D is an N-channel junction field effect transistor, and 3D06C is an N-channel insulated gate field effect transistor.
Semiconductor discrete devices produced in Japan are composed of five to seven parts. Usually only the first five parts are used, and the symbolic meaning of each part is as follows:
Part 1: Use numbers to indicate the number or type of effective electrodes of the device. 0-photoelectric (ie photosensitive) diode triode and combination tube of the above devices, 1-diode, 2 triode or other devices with two pn junctions, 3- other devices with four effective electrodes or three pn junctions, ┄┄and so on.
Part 2: Japan Electronics Industry Association JEIA registration mark. S- indicates a semiconductor discrete device that has been registered with the Japan Electronics Industry Association JEIA.
Part 3: Use letters to indicate the polarity and type of materials used in the device. A-PNP type high frequency tube, B-PNP type low frequency tube, C-NPN type high frequency tube, D-NPN type low frequency tube, FP control pole thyristor, GN control pole thyristor, HN base single junction transistor , JP channel field effect tube, KN channel field effect tube, M-bidirectional thyristor.
Part 4: Use numbers to indicate the serial number registered with the Japan Electronics Industry Association JEIA. Integer of more than two digits-starting with "11", it indicates the serial number registered with the Japan Electronics Industry Association JEIA; devices with the same performance from different companies can use the same serial number; the larger the number, the more recent products.
Part 5: Use letters to indicate the improved product logo of the same model. A, B, C, D, E, F indicate that this device is an improved product of the original model.
For example, 2SK134 is an N-channel MOSFET, and 2SJ49 is a P-channel MOSFET.
FPGA Spartan-XL Family 20K Gates 950 Cells 250MHz 3.3V 208-Pin HSPQFP EP
FPGA XC3000 Family 3K Gates 144 Cells 80MHz 3.3V 100-Pin VTQFP
FPGA Virtex-II Family 1.5M Gates 17280 Cells 750MHz 0.15um Technology 1.5V 575-Pin BGA
FPGA Virtex-II Family 1.5M Gates 17280 Cells 750MHz 0.15um Technology 1.5V 676-Pin FBGA
Xilinx PLCC+8 CPLD/FPGA
Support
