Logic synthesis is the process of transforming the circuit's behavior-level description, especially the RTL-level description into a gate-level expression. For example, VHDL and Verilog synthesis are logic synthesis.
For logic synthesis, it can usually be divided into ASIC synthesis and PLD synthesis according to different processes. ASIC synthesis is based on the ASIC process. Designers can give comprehensive constraints and comprehensive use of component library technology, and generate gate-level netlist files through logic synthesizer compilation and optimization. PLD synthesis is based on the PLD process. Since the PLD process usually prescribes the target PLD device, the designer only needs to give (composite constraints and) the target PLD device. Generally, PLD synthesis is combined with subsequent placement and routing. This is possible because the physical characteristics of the target device are known to the PLD synthesizer.
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 160-Pin HSPQFP EP
FPGA Spartan-XL Family 20K Gates 950 Cells 217MHz 3.3V 100-Pin VTQFP
FPGA Spartan-XL Family 20K Gates 950 Cells 250MHz 3.3V 144-Pin TQFP
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 676-Pin FBGA
FPGA Virtex-II Family 1.5M Gates 17280 Cells 750MHz 0.15um Technology 1.5V 896-Pin FCBGA
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