The SelectIO Interface Wizard is provided in compliance with Xilinx End User License Terms and is provided free with ISE® and Vivado™ software.
Xilinx provides an easy-to-use wizard for configuring SelectIO modules in Xilinx FPGAs.
The LogiCORE™ IP SelectIO™ interface wizard provides an intuitive custom GUI that helps users configure the SelectIO module on Xilinx FPGA to fully meet their design needs. This wizard can generate an HDL wrapper that can be used not only to configure SelectIO modules (such as IOSERDES and IODELAY), but also to connect it to the IO clock primitives in the design. Includes built-in templates to automatically configure SelectIO to support various standard interfaces (SGMII, DVI, camera link, chip-to-chip) and various I/O signaling standards (LVCMOSxx, HSTLxx, SSTLxx).
Support input, output or bidirectional bus
Simplify the creation of clock circuits to drive IO logic
Supports data bus up to 32 bits wide
Optional serialization of data up to 14 bits in DDR mode
Optional data and/or clock delay insertion
Single or dual data rate data
Single-ended or differential standards for clock and/or data.
Access optional primitive port.
Can be used with PlanAhead™ to implement other IO configurations.
Optional phase detector function can be realized.
Use the "Auto Update" feature in CORE Generator to update the core to the latest version in the project.
FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Spartan-3AN Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V Automotive Medical 400-Pin FBGA
CPLD CoolRunner Family 4K Gates 128 Macro Cells 0.5um Technology 5V 100-Pin VTQFP
FPGA XC4000E Family 25K Gates 2432 Cells 0.35um Technology 5V 240-Pin HSPQFP EP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 208-Pin PQFP
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