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JKFF

JKFF(J-K Flip-Flop)  JK flip-flop is a basic circuit unit in digital circuit flip-flop. The JK trigger has the functions of setting 0, setting 1, holding and flipping. Among various integrated triggers, the function of the JK trigger is the most complete. In practical applications, it not only has strong versatility, but also can flexibly convert other types of triggers. D flip-flops and T flip-flops can be formed by JK triggers.

JKFF

Functional description

JK trigger logic diagram as shown on the right

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JK triggers are similar to the most basic RS triggers in triggers. The difference is that RS triggers do not allow R and S to be 1 at the same time, while JK triggers allow J and K to be 1 at the same time. When J and K become 1 at the same time, the output value state will be reversed. That is to say, if it is 0, it becomes 1; if it is 1, it becomes 0. The correspondence table is as follows:

The pulse operating characteristics are shown on the right

There is no one-time change in this trigger, and the input signal can be added before the CP trigger edge changes from 1 to 0.

Into. It can be seen from Figure 7.6.1 that the circuit requires J and K signals to be transmitted to the output terminals of G3 and G4 before the CP signal trigger edge. Therefore, their addition time should be at least one stage earlier than the CP trigger edge. time. This period of time is called the setup time test.

The input signal does not need to be maintained after the negative transition trigger edge arrives, because even if the original J and K signals change, it must be delayed by the first-level NAND gate before being transmitted to the output terminals of G3 and G4. The flip-flop has been determined by the output state of G12, G13, G22, G23 and the original state of the flip-flop. Therefore, this trigger requires the input signal to be maintained for a very short time, which has a high anti-interference ability, and can shorten the tCPH can increase the working speed.

It takes a certain delay time tCPL from the negative transition trigger edge to the stable output state of the flip-flop. Obviously, the delay time should be greater than the delay time of the two-level NOR gate. That is, tCPL is greater than 2.8tpd.

In summary, the edge JK trigger is summarized as follows:

1. The edge JK trigger has functions of set, reset, hold (memory) and counting; 2. The edge JK trigger belongs to the pulse trigger mode, and the trigger flip occurs only on the negative transition edge of the clock pulse; 3. Due to receiving the input signal The work is completed before the falling edge of CP, the flip is triggered on the falling edge, and the trigger is blocked after the falling edge, so there is no change phenomenon, the anti-interference performance is good, and the working speed is fast.


Product category

Master-slave JK trigger

Circuit configuration

The master-slave JK trigger is composed on the basis of the master-slave RS trigger, as shown in Figure 7.5.1. Add a two-input AND gates G11 and G10 to the R and S terminals of the master and slave RS flip-flops respectively, and output the Q terminal and the input terminal as the original S terminal through the AND gate. The input terminal is called the J terminal, and the Q terminal and The output of the input terminal via the AND gate is the original R terminal, and the input terminal is called the K terminal.

working principle

S = JQ and R = KQ can be obtained from the above circuit. Substituting the characteristic equation of the master and slave RS flip-flops gives:

when

When J=1 and K=0, Qn+1=1;

When J=0 and K=1, Qn+1=0;

When J=K=0, Qn+1=Qn;

When J=K=1, Qn+1=~Qn;

From the above analysis, the master-slave JK trigger has no constraints. When J=K=1, the flip-flop flips every time a clock pulse is input. This working state of the flip-flop is called the counting state, and the number of input clock pulses can be calculated from the number of flips of the flip-flop.

Working characteristics

Settling time: refers to the time when the input signal should arrive before the CP signal, expressed by tset. It can be seen from Figure 7.5.5 that the J and K signals only need to arrive no later than the CP signal, so tset=0. Holding time: In order to ensure that the flip-flop is reliably turned over, the input signal needs to be held for a certain time. The holding time is expressed in tH. If the state of J and K is required to remain unchanged during CP=1, and the time of CP=1 is tWH, then tH≥tWH should be satisfied.

Transmission delay time: If the period from the CP falling edge to the stable establishment of the new state at the output is defined as the transmission time, there are: tPLH=3tpd tPHL=4tpd Maximum clock frequency: because the master and slave triggers are It consists of two synchronous RS flip-flops, so it can be known from the dynamic characteristics of the synchronous RS flip-flop that in order to ensure the reliable flip of the main trigger, the duration of the CP high level tWH should be greater than 3tpd. Similarly, in order to ensure that the flip-flop can be reliably turned over, the duration tWL of the CP low level should also be greater than 3tpd. Therefore, the minimum period of the clock signal is: Tc (min) ≥ 6tpd, the highest clock frequency fc (max) ≤ 1/6tpd.

If the J and K flip-flops in Figure 7.5.5 are connected as T flip-flops (that is, J and K are connected to a high level), the maximum clock frequency is even lower. Because the time from the falling edge of CP to the stable establishment of the new state at the output is tPHL≥4tpd, if the duty cycle of the CP signal is 50%, then the highest frequency of the CP signal can only reach fc(max)=1/ 2tPHL=1/8tpd.

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Master-slave falling edge with clear function triggers JK trigger

If Reset=0:

When J=1 and K=0, Qn+1=1;

When J=0 and K=1, Qn+1=0;

When J=K=0, Qn+1=Qn;

When J=K=1, Qn+1=Qn;

If Reset=1:

Regardless of the values of J, K, and Qn, Qn+1=0.

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Integrated trigger

There are many products with integrated JK flip-flop. The following introduces a typical high-speed CMOS dual JK flip-flop HC76. The flip-flop contains two identical JK flip-flops, both of which have preset and clear inputs, and belong to the edge flip-flop triggered by a negative edge. The logic symbols and pin assignments are shown in Figure 7.5.6 below. Its function table is shown in Table 7.5.1. If there are multiple triggers in an integrated device, usually add numbers in front of (or behind) the symbol to indicate the input and output signals of different triggers. For example, C1 and 1J and 1K belong to the same trigger.

In summary

The main and slave JK triggers are summarized as follows:

1. Master-slave JK trigger has set, reset, hold (memory) and count functions;

2. The master-slave JK trigger belongs to the pulse trigger mode, and the trigger flip occurs only on the negative transition edge of the clock pulse;

3. There are no constraints, but there is a change.

4. The reason for a change is that during CP=1, the main trigger has been receiving data, but under certain conditions (Q=0, CP=1, there is a positive edge interference or Q at the J terminal during CP=1 =1, there is a positive jump edge interference at the K terminal during CP=1), and the corresponding change cannot be completely caused by the change of the input signal, so as to affect the non-correspondence between the trigger state and the input signal.

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