HDPLD(High Density PLD), It includes three parts:
1.i/o unit
The input/output circuit, which includes input and output registers, tri-state gates, multiplexers, output slew rate control circuit, and boundary scan circuit, has more functions.
2. Basic logical unit block blb
It is the smallest unit to realize logic function. Note: This part of the company has different names, lattice is the general logic array block (glb—generic logic block), altrra is the logic element (le-logic element), and xilinx is called the configurable logic block (clb—configrable logic block) . The scale of these basic logical unit blocks is also different, and it will be convenient for design when the scale is large. When using, it should be selected according to different system size requirements.
3. Programmable interconnect resources (pi-programmable interconnect)
It connects the functions described by each unit to form a complete digital system, and connects the input/output to specific i/o units. The design of this part requires experience and craftsmanship. The quality of the pi design will be related to the use efficiency of the pld and the stable operation of the pld device.
1. Development foundation: developed from the gate array;
2. Internal basic circuit: a series of logic gates, flip-flops and a large number of programmable "AND" arrays, programmable "OR" arrays are integrated inside;
3. Integrated technology cmos technology, uveprom, eeprom, flash memory, sram adopted;
4. Use technical users to directly perform logic programming operations on the internal structure of the device;
5. Main features: ① The logic function is realized by programming, so that most of the hardware design of the digital system circuit is converted into software design (programming);
② With a large number of equivalent programming gates (hundreds to millions of gates), basically can meet the chip design of various digital electronic systems;
③ The speed is very fast, because the function is determined by the hardware programming of the internal circuit;
④Users can not use it directly, they must be programmed by the development software → download to specific chip;
According to programming process: fuse and anti-fuse process, uveprom process e2prom, flash memory process sram programming process.
Divided by programming mode: isp mode (programmable in the system), icr mode (in circuit configuration mode), hardware programmer programming mode.
Divided by device structure: cpld device, fpga device
Common name: epld—erasable programmable logic device
hdpld— high density programmable logic device
ldpld—low density programmable logic device
isppld—in system programmable programmable logic device
cpld—complex programmable logic device
fpga—field programmable logic device
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 56-Pin CSBGA
Xilinx BGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
Support
