Global routing refers to the overall planning of the routing of the entire chip, in order to determine that even a very large chip design can achieve its final routing plan.
Global routing is to prepare for detailed routing (or final routing). It must first formulate the goal of global wiring, and then make specific plans based on the characteristics of the design. For example, the design that requires wiring can be a chip or a large module with a custom design. The shape of the chip can be square or rectangular.
When planning the layout of the chip, we must first understand its characteristics. The chip is usually composed of standard units and blocks.
Global routing is fast and has a short time, which can speed up convergence. It plans for the final routing that takes a long time. If the global wiring finds problems, people can solve the adjustments in time without having to spend a long time to do the final wiring and other follow-up work. The main goals of global routing are:
(1) Make the total connecting line the shortest.
(2) Evenly distributed wiring will not cause local congestion.
(3) Minimize the critical path delay and observe the timing rules.
(4) Understand the requirements of signal integrity and avoid cross talks.
(5) Keep the BUS bus connected, etc.
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 44-Pin VQFP
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 56-Pin CSBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
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