FPLA (Field Programmable Logic Array) Field Programmable Logic Array is a type of programmable logic device (PLD), a so-called "logic block" of semiconductor devices containing programmable logic elements, and programmable interconnects. Logic blocks can be programmed to perform basic logic gate functions, such as AND, XOR, or more complex combinations. In most FPLDs, logic blocks also include memory molecules, which may be simple triggers or more complete blocks Memory. Hierarchical programmable interconnects, so that logic blocks need to be interconnected, the system designer is a bit like a programmable chip logic block and interconnects can be programmed by the customer or designer, after the FPLD is manufactured to execute Any logic function, hence the name "field programmable".
In 1992, Xilinx's advanced field programmable logic device EPLD, based on EPROM, technology and CMOS technology, and added high-speed functional modules and high-density modules, is a powerful supplement to FPGA, the number of logic gates from 300-4000 gates, pins Count from 20-288 feet.
Contains 9 programmable "AND" / "OR" array driven macro cell any one pin input or macro cell output can be connected to any other cell.
Strong wiring function:
The unique structure makes its interconnection rate very high, and no manual wiring is needed to optimize speed and density. Predictable logic and interconnection timing delay;
The timing delay is uniform. It can be used to predict the electrically erasable and reprogrammed devices with a monolithic structure before the logic is implemented. No external ROM is required, and the confidentiality is greatly enhanced.
Especially suitable for completing all kinds of algorithms and other combinational logic, and more suitable for completing multi-sequence logic.
Typical products: XC7000, such as XC7336, XC7354, XC7372, etc.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 896-Pin FCBGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 100-Pin VTQFP
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 56-Pin CSBGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 44-Pin PLCC
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
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