EPLD: (Erasable Programmable Logic Device) An erasable and editable logic device is an integrated circuit that includes a series of programming logic devices that do not need to be connected again.
The erasable programmable logic device EPLD is a large-scale programmable logic device introduced by Aitera in the mid-1980s. The basic structure of EPLD is not fundamentally different from GAL, but its integration density is much higher than GAL, which enables it to realize more logic functions in one chip. The representative EPLDs are Atmel's ATV750, ATV2500 and ATV5000.
Circuit logic function description
The logic function description of PLD devices is generally divided into schematic description and hardware description language description. The schematic description is an intuitive and convenient method, which can directly implement the functions realized by existing small-scale integrated circuits with PLD devices, and It is not necessary to describe existing circuits in language. However, the circuit diagram description method cannot be concise; the hardware description language description is another description method for programmable device design. The language description may accurately and concisely represent the logic function of the circuit. It is now widely used in the PLD design process, and there are The trend is even more popular. The commonly used hardware description languages are ABEL, VHDL, Verilog, etc. Among them, ABEL is a simple hardware description language that supports logical descriptions such as Boolean equations, truth tables, and state machines. It is suitable for counters, translations, etc. Description of logic functions such as encoders, arithmetic circuits, and comparators; VHDL language is a high-level language for circuit design. It has a powerful language structure and can describe complex logical controls with concise and clear source code. Verilog language is a behavior description language. Its programming structure is similar to the C language in computers. When describing complex logic designs, it is very concise and has strong logic description and simulation capabilities. It is the mainstream of future hardware design languages.
Computer software programming and simulation
Regardless of whether the logic described in the hardware description language or the logic described in the schematic diagram must be compiled by computer software, its description is converted into a simplified Boolean algebraic expression (that is, the most simple AND or expression) Then, compile the software and adapt the expression to the specific device according to the characteristics of the device, and finally form the fuse file of the PLD device (usually called JEDEC file, referred to as JED file for short).
Usually, before downloading the logic designed by the user to a specific device, in order to check whether the design result is correct, it can usually be simulated by computer software to check whether the design result is consistent with the design requirements.
Download the JED file to the PLD device through the programmer
The fuse wire file formed in the previous step must be downloaded to the PLD device to achieve the design requirements. The fuse wire file download generally must be downloaded through the programmer.
The programmer is a professional device specially used for programming programmable devices (such as PROM, EEPROM, GAL, CPLD, PAL, etc.). Common programmers include the ALL series of Taiwan Heluo Company and Nanjing Celtic Company. Super series, etc. The programmer usually downloads the JED file to the programmer through the computer's parallel printer, and the programmer then writes the JED file into the device according to the characteristics of the device, so as to achieve the purpose of downloading. The following figure shows the design process of PLD.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 896-Pin FCBGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 48-Pin QFN EP
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um Technology 1.8V 56-Pin CSBGA