DMA (Direct Memory Access) is an important feature of all modern computers. It allows hardware devices of different speeds to communicate without relying on a large number of CPU interrupt loads. Otherwise, the CPU needs to copy the data of each segment from the source to the scratchpad, and then write them back to the new place again. During this time, the CPU is unavailable for other tasks.
DMA transfer copies data from one address space to another address space. When the CPU initiates this transfer action, the transfer action itself is carried out and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Operations like this do not delay the processor, but can be rescheduled to handle other tasks. DMA transfer is very important for high-performance embedded system algorithms and networks.
When realizing DMA transmission, the bus is directly controlled by the DMA controller. Therefore, there is a problem of bus control transfer. That is, before the DMA transfer, the CPU should hand over the bus control to the DMA controller, and after the DMA transfer is completed, the DMA controller should immediately return the bus control to the CPU. A complete DMA transfer process must go through 4 steps: DMA request, DMA response, DMA transfer, and DMA end.
Request
The CPU initializes the DMA controller and issues an operation command to the I/O interface, and the I/O interface issues a DMA request.
Response
The DMA controller determines the priority and shielding of the DMA request, and makes a bus request to the bus adjudication logic. When the CPU executes the current bus cycle, the bus control can be released. At this time, the bus arbitration logic outputs a bus response, indicating that the DMA has responded, and notifies the I/O interface to start the DMA transfer through the DMA controller.
Transmission
After the DMA controller obtains the bus control right, the CPU immediately suspends or only performs internal operations. The DMA controller outputs read and write commands to directly control the RAM and I/O interface for DMA transfer.
Under the control of the DMA controller, data is directly transferred between the memory and the external device, and no central processor is required during the transfer. At the beginning, you need to provide the starting position and data length of the data to be transferred.
End
When the specified batch of data transfer is completed, the DMA controller releases the bus control right and sends an end signal to the I/O interface. When the I/O interface receives the end signal, on the one hand, it stops the I/O device, on the other hand, it makes an interrupt request to the CPU, so that the CPU is free from the state of intervention, and performs a section to check the correctness of the DMA transfer operation. Code. Finally, carry out the original program with the results and status of this operation.
It can be seen that the DMA transfer method does not require the CPU to directly control the transfer, nor does it have the process of retaining the scene and restoring the scene as the interrupt processing method. Through the hardware, a direct path for data transfer is opened for the RAM and I/O devices, so that the efficiency of the CPU is greatly improved. improve.
The emergence of DMA technology allows peripheral devices to directly access memory through the DMA controller, while the CPU can continue to execute programs. So how does the DMA controller and the CPU use memory in time-sharing? Usually the following three methods are used: (1) stop the CPU from accessing the memory; (2) cycle stealing; (3) DMA and the CPU alternately access the memory.
Stop the CPU from accessing memory
When the peripheral device requests to transfer a batch of data, the DMA controller sends a stop signal to the CPU, requesting the CPU to give up the right to use the address bus, data bus, and related control bus. After the DMA controller obtains the bus control right, it starts data transfer. After a batch of data is transferred, the DMA controller informs the CPU that the memory is available and returns the bus control to the CPU. Figure (a) is a time chart of this transmission method. Obviously, in this DMA transfer process, the CPU is basically in a non-working state or holding state.
Advantages: Simple control, it is suitable for group transmission of equipment with high data transmission rate.
Disadvantages: In the stage of DMA controller accessing memory, the efficiency of memory is not fully utilized, and a considerable part of the memory work cycle is idle. This is because the interval between peripheral devices transmitting two data is always greater than the memory storage period, even for high-speed I/O devices. For example, a floppy disk requires about 32us to read an 8-bit binary number, and the storage period of semiconductor memory is less than 0.5us, so many idle storage periods cannot be used by the CPU.
Cycle diversion
When the I/O device has no DMA request, the CPU accesses the memory as required by the program; once the I/O device has a DMA request, the I/O device embezzles one or several memory cycles.
Time chart of this transmission method:
I/O devices may encounter two situations when DMA transfer is required:
(1) At this time, the CPU does not need to visit the internal, such as the CPU is executing a multiplication instruction. Due to the long execution time of the multiplication instruction, there is no conflict between the I/O access and the CPU access, that is, the I/O device stealing one or two memory cycles has no effect on the CPU execution program.
(2) When the I/O device requests an internal visit, the CPU also requests an internal visit, which creates an internal visit conflict. In this case, the I/O device internal visit takes precedence, because there is a time requirement in the I/O internal visit, the previous one I/O data must be accessed before the next access request. Obviously, in this case, the I/O device steals one or two memory cycles, which means that the CPU has delayed the execution of the instruction, or more specifically, inserts a DMA request during the CPU's execution of the in-access instruction, and embezzles a Two memory cycles. Compared with the DMA method of stopping CPU access, the method of cycle stealing not only achieves I/O transfer, but also better utilizes the efficiency of memory and CPU. It is a widely adopted method. However, every cycle of I/O device diversion has the process of applying for bus control, establishing line control, and returning bus control, so transferring a word takes one cycle for memory, but it is generally necessary for DMA controllers. 2-5 memory cycles (depending on the delay of the logic circuit). Therefore, the method of cycle misappropriation is suitable for the case where the read/write cycle of the I/O device is greater than the memory storage cycle.
DMA and CPU access memory alternately
If the working cycle of the CPU is much longer than the memory access cycle, then the method of alternating access can be used to make the DMA transfer and the CPU play the highest efficiency at the same time.
The time chart of this transmission method is as follows:
This chart is a detailed time chart of DMA and CPU alternate visits. Assuming that the CPU work cycle is 1.2us and the memory access cycle is less than 0.6us, then a CPU cycle can be divided into two sub-cycles of C1 and C2, where C1 is dedicated to the DMA controller and C2 is dedicated to the CPU.
This method does not require the application, establishment, and return process of the bus usage right. The bus usage right is allocated through C1 and C2. The CPU and the DMA controller each have their own control registers such as internal address registers, data registers, and read/write signals. In the C1 cycle, if the DMA controller has an in-access request, it can send signals such as address and data to the bus. In the C2 cycle, if the CPU has an internal request, it also transmits signals such as address and data. In fact, for the bus, this is a multiplexer controlled by C1, C2, this transfer of bus control power takes almost no time, so the efficiency of DMA transfer is very high.
This transfer method is also called "transparent DMA" mode. The reason is that this DMA transfer is like transparent glass to the CPU, without any feeling or influence. Working in a transparent DMA mode, the CPU neither stops the main program running nor enters the waiting state, which is an efficient working method. Of course, the corresponding hardware logic is more complicated.
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