Used to control whether the internal pull-up resistor of the user I/O used during configuration works。
This lends power savings to High-end Communication equipment and speed to battery operated devices.
This lends power savings to High-end Communication equipment and speed to battery operated devices.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 575-Pin BGA
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 896-Pin FCBGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 100-Pin VTQFP
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