Used for search driving
For Stratix® III and Stratix IV devices, the TDO output pin and all the JTAG input pins are powered by the VCCPD supply of I/O Bank 1A.
VCCPD can be powered by 2.5V, 3.0V, or 3.3V in Stratix III devices.
VCCPD can be powered by 2.5V or 3.0V in Stratix IV devices.
The VCCPD voltage for each bank is dependent on the voltage used for VCCIO. Refer to the respective Device Pin Connection Guidelines for details.
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 304-Pin HSPQFP EP
This lends power savings to High-end Communication equipment and speed to battery operated devices.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 575-Pin BGA
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 56-Pin CSBGA