This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > GNDD_PLL

GNDD_PLL

PLL digital ground

With the development of digital circuit technology, digital phase-locked loops have been widely used in various aspects such as modulation and demodulation, frequency synthesis, FM stereo decoding, color subcarrier synchronization, and image processing. The digital phase-locked loop not only absorbs the advantages of high reliability, small size, and low price of digital circuits, but also solves the shortcomings of analog phase-locked loops such as DC zero drift, device saturation, and susceptibility to changes in power and ambient temperature. The real-time processing capability of discrete samples has become the development direction of phase lock technology.

Equipment introduction

With the development of digital circuit technology, digital phase-locked loops have been widely used in various aspects such as modulation and demodulation, frequency synthesis, FM stereo decoding, color subcarrier synchronization, and image processing. The digital phase-locked loop not only absorbs the advantages of high reliability, small size, and low price of digital circuits, but also solves the shortcomings of analog phase-locked loops such as DC zero drift, device saturation, and susceptibility to changes in power and ambient temperature. The real-time processing capability of discrete samples has become the development direction of phase lock technology.

The phase-locked loop is a phase feedback control system. In the digital phase-locked loop, since the error control signal is a discrete digital signal instead of an analog voltage, the controlled output voltage change is discrete rather than continuous; in addition, The components of the loop are also all realized by digital circuits, so this kind of phase-locked loop is called an all-digital phase-locked loop (DPLL for short).

The digital phase-locked loop is mainly composed of phase reference extraction circuit, crystal oscillator, frequency divider, phase comparator, pulse compensation gate and so on. The frequency of the signal output by the frequency divider is very close to the required frequency, and the phase reference signal extracted from the signal is sent to the phase comparator at the same time. The comparison result shows that when the local frequency is high, an input is erased through the compensation gate The pulse of the frequency divider is equivalent to a decrease in the local oscillation frequency; on the contrary, if it shows that the local frequency is low, a pulse is inserted between the two input pulses at the input of the frequency divider, which is equivalent to the increase of the local oscillation frequency, thereby achieving synchronization.

The structure of a digital phase-locked loop is generally composed of a digital phase detector (DPD, Digital Phase Detector), a digital loop filter (DLF, Digital Loop Filter), and a digital voltage-controlled oscillator (DCO, Digital Control Oscillator) It consists of three parts.

(1) Digital loop phase detector (DPD)

Digital phase detector, also called sampling phase detector, is used to compare the phase of the input signal with the output signal of the voltage-controlled oscillator, and its output voltage is a function corresponding to the phase difference between the two signals. It is a key component in the phase-locked loop. The form of the digital phase detector can be divided into: zero-crossing sampling phase detector, flip-flop digital phase detector, lead-lag digital phase detector and Nyquist rate Sampling phase detector.

(2) Digital loop filter (DLF)

The digital loop filter suppresses the input noise in the loop and adjusts the correction speed of the loop. Digital filter is a kind of specialized technology, there are various structural forms and design methods. The purpose of introducing a digital loop filter is the same as that of introducing a loop filter into an analog phase-locked loop, which is to introduce a loop as a correction network. Therefore, a reasonable design of the digital loop filter and selection of an appropriate digital filter structure can make the DPLL meet the predetermined system performance requirements.

(3) Digital voltage controlled oscillator (DCO)

Numerically controlled oscillator, also known as digital clock. Its position in the digital loop is equivalent to the voltage controlled oscillator (VCO) in the analog phase-locked loop. However, its output is a pulse sequence, and the period of the output pulse sequence is controlled by the correction signal sent by the digital loop filter. Its control feature is: the correction signal obtained at the previous sampling moment will change the pulse time position of the next sampling moment.

Working principle

The basic working process of the all-digital phase-locked loop is as follows:

(1) Suppose the input signal Ui(t) and the local oscillator signal (digital voltage-controlled oscillator output signal) Uo(t) are the sine and cosine signals respectively, and they are compared in the digital phase detector, the output of the digital phase detector It is a voltage Ud(t) proportional to the phase difference between the two.

(2) The digital loop filter removes the high-frequency components in the output of the digital phase detector, and then adds the output voltage Uc(t) to the input of the digital voltage-controlled oscillator. The frequency of the local oscillator signal of the digital voltage-controlled oscillator follows Changes with changes in the input voltage. If the two frequencies are inconsistent, the output of the digital phase detector will produce a low-frequency change component, and the DCO frequency will change through a low-pass filter. As long as the loop is properly designed, this change will make the frequency of the local oscillator signal Uo(t) consistent with the frequency of the digital phase detector input signal Ui(t).

(3) Finally, if the frequency of the local oscillator signal is exactly the same as the frequency of the input signal, the phase difference between the two will remain a constant value, and the output of the digital phase detector will be a constant DC voltage (ignoring high-frequency components) , The output of the digital loop filter is also a DC voltage, and the frequency of the DCO will also stop changing. At this time, the loop is in a "locked state".

ASSOCIATED PRODUCTS

  • XC4028XL-09HQ240C

    XC4028XL-09HQ240C

    FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 240-Pin HSPQFP EP

  • XC2C64-7CP56C

    XC2C64-7CP56C

    This lends power savings to High-end Communication equipment and speed to battery operated devices.

  • XC2C64-7VQ100I

    XC2C64-7VQ100I

    This lends power savings to High-end Communication equipment and speed to battery operated devices.

  • XC2V1500-4BG575C

    XC2V1500-4BG575C

    FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 575-Pin BGA

  • XC2V1500-4FFG896I

    XC2V1500-4FFG896I

    FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 896-Pin FCBGA

FPGA Tutorial Lattice FPGA
Need Help?

Support

If you have any questions about the product and related issues, Please contact us.