Verilog

Development History

Verilog was founded by the engineers of Gateway Design Automation in late 1983. At that time, Gateway Design Automation was also called Automated Integrated Design Systems. In 1985, the company changed its name to the former. The company's Phil Moorby (Phil Moorby) completed the main design work of Verilog. In 1990, Gateway Design Automation was acquired by Cadence.

In the early 1990s, the Open Verilog International (Open Verilog International, OVI) organization (now Accellera) was established, and Verilog was open to the public domain. In 1992, the organization sought to incorporate Verilog into the Institute of Electrical and Electronics Engineers standards. Eventually, Verilog became the 1364-1995 standard of the Institute of Electrical and Electronics Engineers, commonly known as Verilog-95.

Designers found some improvements in the use of this version of Verilog. In order to solve the problems reflected by users in the process of using this version of Verilog, Verilog has been revised and expanded, and this part of the content was later submitted to the Institute of Electrical and Electronics Engineers again. This expanded version later became the Institute of Electrical and Electronics Engineers 1364-2001 standard, commonly known as Verilog-2001. Verilog-2001 is a major improved version of Verilog-95. It has some new practical functions, such as sensitive lists, multi-dimensional arrays, generated statement blocks, and named port connections. Currently, Verilog-2001 is the most mainstream version of Verilog and is supported by most commercial electronic design automation software packages.

In 2005, Verilog updated again, the Institute of Electrical and Electronics Engineers 1364-2005 standard. This version is only a minor correction from the previous version. This version also includes a relatively independent new part, namely Verilog-AMS. This extension allows traditional Verilog to model integrated analog and mixed-signal systems. What is easily confused with the Institute of Electrical and Electronics Engineers 1364-2005 standard is SystemVerilog (the Institute of Electrical and Electronics Engineers 1800-2005 standard), which is a superset of Verilog-2005. It is a hardware description language and a hardware verification language. (For the verification requirements, the object-oriented features are particularly strengthened) An integration.

In 2009, IEEE 1364-2005 and IEEE 1800-2005 were merged into IEEE 1800-2009 and became a new and unified SystemVerilog hardware description and verification language (HDVL).

Design

To describe complex hardware circuits, designers always divide complex functions into simple functions, and modules are the basic structure that provides each simple function. Designers can take the "top-down" approach and divide complex functional modules into low-level modules. This step is usually done by the chief designer at the system level, while the lower-level modules are done by the designers at the next level. The top-down design method is conducive to system-level hierarchical division and management, and improves efficiency and reduces costs. The "bottom-up" approach is the reverse of the "top-down" approach.

The basic design unit that uses Verilog to describe hardware is a module. The construction of complex electronic circuits is mainly achieved through the interconnection and calling of modules. Modules are included in the keywords module and endmodule. Actual circuit components. The module in Verilog is similar to the function in C language. It can provide input and output ports. It can call other modules by instance, and can also be called by other module instances. The module can include combinational logic and process timing. For example, a multiplexer with four choices can be described by a module. It has two bit-selected input signals, four data inputs, and an output terminal, which can be expressed in Verilog as:

module mux (out, select, in0, in1, in2, in3);

output out;

input [1:0] select;

input in0, in1, in2, in3;

//Specific register transfer level code

endmodule

Designers can use a top-level module to test by calling the above module by example. This top-level module is often referred to as "Testbench". In order to maximize the functional verification of the circuit's logic, the test code needs to cover as many statements, branches, conditions, paths, triggers, and state machine states as possible by the system. Verifiers need to create enough input in the test platform Encourage and connect to the input of the module under test, and then check whether the output of the module performs as expected (such as SystemVerilog's hardware verification language can provide a data structure specifically optimized for verification, and verify it by random testing, which is highly complicated The verification of integrated circuit design can play a key role). When an instance calls a module, it is necessary to arrange the port connections in the order in which the module is declared. This top-level module does not need to be called by the outside world, so it has no input and output ports:

module tester;

reg [1:0] SELECT;

reg IN0, IN1, IN2, IN3;

wire OUT;

mux my_mux (OUT, SELECT, IN0, IN1, IN2, IN3); //The instance calls the mux module, this instance is named my_mux

initial //Need to simulate the excitation code

begin

*******

end

endmodule

In this test platform module, the designer can set the input signal and signal monitoring program during the simulation, and then observe whether the output during the simulation meets the requirements, so that you can understand whether the design has met expectations.

In the example reference to the module, the input variables are listed in the order in which the original module was declared. In addition, you can also use or use a named port connection. In this way, the order of the ports can be different from the original module declaration, and even some ports can not be connected:

mux my_mux (

.out(OUT),

.select(SELECT),

.in0(IN0),

.in1(IN1),

.in2(IN2),

.in3(IN3));//Use named port connection, outside the bracket is the port when the module is declared, inside the bracket is the actual port connection // outside the bracket is equivalent to the C formal parameter, and the bracket is equivalent to the actual parameter

endmodule

The situation described above is that the test variables of the top module of the test platform are directly connected to the designed functional module. The test platform can also be in another form, that is, the test platform is not directly connected to the designed functional module, but under this test platform, the excitation module and the functional module are connected to each other through the wire network at the same abstract level. Both types of test platforms can complete the testing of functional modules. The large-scale circuit system is realized by the connection and transfer between different modules at various levels to achieve complex functions.

Language element

The original intention of Verilog is to be a hardware description language whose basic grammar is similar to C language. This is because the C language was widely used in many fields at the beginning of Verilog design, and many language elements of the C language have been used by many people. A hardware description language similar to C language can make it easier for circuit designers to learn and accept. However, there are still many differences between Verilog and C language. In addition, as a hardware description language that is different from ordinary computer programming languages, it also has some unique language elements, such as vector-shaped wire nets and registers, and non-blocking assignments in the process. In general, designers with C language will be able to quickly master the Verilog hardware description language.

Basic specifications

Whitespace

White space refers to spaces in the code (the corresponding escape identifier is \b), tabs (\t), and newlines (\n). If these whitespace characters appear in the string, they can be ignored. In addition, other whitespace characters in the code will be treated as delimited identifiers when compiled, that is, the use of 2 spaces or 1 space has no effect. However, using appropriate spaces in the code can make the appearance of the upper and lower lines of code consistent (for example, make the assignment operators in the same vertical column), thereby improving the readability of the code.

Annotate

In order to facilitate the modification of the code or other people's reading, designers usually add comments to the code. Like C language, there are two ways to write notes. The first is a multi-line comment, that is, the comment starts from /* and does not end until */; the other is a single-line comment, the comment starts from //, and the content from here to the end of this line will be recognized as a comment by the system.

Some electronic design automation tools will recognize comments written in a special format in the code and contain certain pre-agreed keywords, and extract useful information from these comments. These notes are not for human reading, but provide additional information about design projects to third-party tools. For example, some logic synthesis tools can read comprehensive constraint information from comments.

Case sensitivity

Verilog is a case-sensitive hardware description language. Among them, all its system keywords are lowercase.

Identifiers and reserved words

The characters used to define the name of the language structure in the Verilog code are called identifiers, including variable names, port names, module names, and so on. Identifiers can be represented by letters, numbers, underscores, and dollar signs ($). However, the first character of the identifier can only be letters, numbers, or underscores, not the dollar sign, because the identifier starting with the dollar sign conflicts with the reserved words of the system task.

Similar to many other programming languages, Verilog also has many reserved words (or keywords), and user-defined identifiers cannot be the same as reserved words. Verilog reserved words are all lowercase. Variable types such as wire, reg, integer, etc., initial, always, etc. that represent processes, and all other system tasks and compilation instructions are keywords. You can consult the official literature for a complete list of keywords.

Escape identifier

An escape identifier (also known as an escape character) is a special programming language structure that starts with \ and ends with a blank character. This structure can be used to represent content that is easily the same as the system language structure (for example, "is used to represent a string in the system. If the content of the string itself contains a double quote in the same form, then you must use the Identifier). The following lists several commonly used escape identifiers. In addition, you can also add ASCII characters after the backslash, this escape identifier is equivalent to a character. Commonly used The meaning identifiers are \n (line feed), \t (tab stop), \b (space), \\ (backslash), \" (double quotes in English), etc.

Wire Net and Register

All variables used by Verilog belong to two basic types: line network type and register type.

The wire network is similar to the wire we actually use. Its value can only be determined by continuous assignment, which is determined by the drive source connected to the right side of the assignment. The value of the wire net before initialization is x (trireg-type wire net is an exception, it is equivalent to a capacitor capable of storing charge). If the drive source is not connected, the current value of the network variable is z, which is the high-impedance state. The variables of the line network type are as follows: wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1, trireg, of which wire is most commonly used as a general circuit connection, while other types are used for Build a bus, that is, the situation where multiple drive sources are connected to a line network, or build a power supply, ground, etc. When the module's port is declared, if the type is not clearly indicated, then the port will be implicitly declared as wire type. Therefore, you should pay attention to whether it is necessary to add the reg keyword when declaring the output port. Take the following code snippet as an example:

module my_moule (out1, out2, in1, in2); //The module has two output ports

output reg out1; //out1 port is declared as reg type, it can save the current value

output out2; //out2 port is implicitly declared as wire type, its value must be maintained by continuous assignment statement

endmodule

Unlike a register, it can save the current value until another value is assigned to it. In the process of maintaining the current value, there is no need for the drive source to act on it. If no value is assigned to the register variable, its initial value is x. The register type variable in Verilog is different from the real hardware register. It refers to a variable that stores a value. If you want to assign a variable in a process (initial process or always process), the variable must be of the register type. There are several types of register variables: reg (regular register), integer (integer), time (time), real (real number), of which reg is most commonly used as a general register. Using the array of register variables, ROM can also be modeled.

Regarding the selection of the line network type or register type, certain regulations need to be met. The input port of the module can be connected to the external line network or register type variables, but the output port of this module can only be connected to the external line network. To make it simpler, at the signal connection point of the two modules, the party providing the signal can be a register or a wire net, but the party receiving the signal can only be a wire net. In addition, the variables assigned in the initial and always procedure code blocks must be of the register type, while the objects of continuous assignment can only be variables of the line network type.

Digital representation

In Verilog, when the type of a variable is determined, that is, it is already known that it is a register type or a line network type, when assigning specific values to it, you need to use the numeric representation method described below. The basic grammatical structure of digital representation is <bit width>'<symbol of number system><value>. Among them, the bit width is the number of digits of the corresponding binary number equal to the data size plus the number of digits used for the placeholder, this digit needs to be expressed in decimal. Bit width is optional. If no bit width is specified, the default data bit width is related to the emulator (minimum 32 bits); the number system needs to be represented by letters, h corresponds to hexadecimal, d corresponds to decimal, o corresponds to octal , B corresponds to binary. If no number system is specified, the default data is a decimal number. E.g:

12'h123: Hexadecimal number 123 (use 12 digits)

20'd44: decimal number 44 (use 20 digits, high digits are automatically filled with 0)

4'b1010: binary number 1010 (use 4 bits)

6'o77: octal number 77 (using 6 digits)

If the highest digit of a certain number is x or z, then the system will automatically use x or z to fill in the higher digits that are not occupied. If the highest bit is otherwise, the system will automatically use 0 to fill in the higher bits that are not occupied.

In addition, if you need to use reg to represent negative numbers, you can add a negative sign before the bit width, but you need to pay attention to the two's complement of the negative number you need. In order to prevent errors, you can directly use integer integer or real number, both are signed numbers, and then use the decimal number omitting the bit width and number system to represent negative numbers.

vector

The data in vector form is a special kind of data of Verilog relative to C language, but this kind of data is very important in hardware description language. In Verilog, scalar means a variable that has only one binary bit, while a vector represents a variable that has multiple binary bits. If the bit width is not specified, the system defaults it to scalar.

In a real digital circuit, such as a carry adder that adds two four-bit binary numbers, we can find that one of the numbers is connected to the adder through four wires (each line represents one of the four bits) Up. We can use a vector to represent this multi-digit number, and use the components of this vector to represent "four wires", that is, one of the four bits. The advantage of this is that you can easily select one (bit selection) or multiple (field selection) of the Verilog code elsewhere. Of course, if no bit selection or field selection is performed, the entire multi-digit number is selected.

The square brackets are needed to represent the vector. The first number in the square brackets is the sequence number of the first component of the vector, and the second number is the sequence number of the last component of the vector, separated by a colon. The serial number of the vector component does not have to start from 0 like the C language array, but in order to be consistent with the representation of the high and low bits of the binary number in the digital circuit, we often let the lowest bit be 0 (that is, for a four-bit binary number, the highest bit is The third place, the next highest place is the second place, the next lowest place is the first place, and the lowest place is the zeroth place), of course, this is just a habit. For example, the four-bit binary number mentioned above is represented by a vector as:

wire [3:0] input_add; //Declare a 4-bit wire vector named input_add

wire [4:1] input_add1; //It is also a 4-bit wire vector, but the component number is from 4 to 1

wire [0:3] input_add2; //It is also a 4-bit wire vector, but the component number is from 0 to 3

After the above vector declaration, we can easily select some of the components to operate. Please note that the position of the square brackets used for field selection is after the vector name, and the numbers in the square brackets are the required number of digits. For example, we can perform the following operations:

input_add [3] = 1'b1; //Assign 1 to the third bit (most significant bit) of input_add vector

input_add [1:0] = 2'b01; //Assign 0 and 1 to the 1st and 0th bits of the input_add vector (lowest two bits)

When assigning to a vector, if the right digit width is larger than the left variable, the extra digits are discarded; if the right digit width is smaller than the left variable, not enough digits are filled with zeros.

Logic gate level description

The level of abstraction described at the logic gate level is lower than the transistor level. Actual hardware circuits are often built on the basis of logic gate-level netlists, and designers often design at a higher level of abstraction. Nevertheless, the design of the logic gate level is still closer to the real circuit form. Verilog provides a series of logic gate primitives (Primitive) for users to use. For example, NOT, AND, OR, OR, NOR, NOR, XOR, XNOR. Logic gate primitives are similar to modules and can be used by instance reference.

Transistor level description

Verilog's ability to describe circuits at a low level of abstraction is an important feature of it. Verilog provides a variety of transistor-level (also called switching-level) element types, including N-type metal oxide semiconductor field effect transistors (keyword nmos), P-type metal oxide semiconductor field effect transistors (keyword pmos), Complementary metal oxide semiconductor (keyword cmos), complementary metal oxide semiconductor with impedance (keyword rcmos), power supply unit (keyword supply1), grounding unit (keyword supply0), etc. All transistors can be set to delay properties. Designers can use these low-level abstraction components to construct the required logic gates or directly constitute other high-level components.

Delay

Logic gate and transistor delay

Real hardware circuits inevitably have delays. In Verilog, you can describe the delay information of logic gates and transistors. You can specify a time for the delay of the component, and then use this time for the rise, fall, and shutdown delays; you can also specify the rise delay and fall delay in sequence, and the shutdown delay takes the smaller of the two; of course, it can also be Specify a time for rise, fall, and shutdown. For example, the following code adds three delay times to the AND gate instance, corresponding to rising, falling, and shutting down:

and #(1, 2, 3) my_and (out, in1, in2);

The delays of logic gates and transistors are "inertial delays". What it means is that after the logic gate and the transistor get an external input, the result will be presented on the output after a specified time delay. During the delay, if the input changes, but the duration of this signal is less than the specified delay time, it will not affect the output of the logic gate and transistor; if the duration of this signal is greater than the specified delay time, the previous results will not Presented at the output, the result after changing the input signal will be presented at the output after a delay

Verilog also allows designers to set the maximum value, typical value, and minimum value for each delay time, and one of them can be selected by compiling code during the compilation phase.

Line delay

When declaring or continuously assigning a line network, you can add delay information to the line network. In this way, all expressions that are continuously assigned to the wire net will immediately calculate the result, but this result will only be assigned to the wire net after the delay time. If the result of the expression on the right changes during this delay time, the result of the expression used for assignment is the changed one. In addition, if the pulse width of the input variable changes less than the delay time, the change will not affect the output. This delay is called "inertial delay", as is the delay of logic gates and transistors.

Process delay

The process delay is described in the previous section on delay timing control. Delays in procedure assignment statements are mainly divided into regular delays (also known as external delays) and embedded delays (also known as internal delays). The former delays first, and then calculates expressions and assigns variables to the left; the latter Calculate the expression immediately, and then assign the result to the variable on the left after a delay.

Path delay

The designer can describe the path delay between the keywords specify and endspecify in the module. Unlike component delay, path delay refers to the delay time required for a signal to pass between two register type or line type variables. The conditional structure can be used in the specify code block to select the required delay time value according to the situation. The same as the element delay, the delay time value can specify the rise, fall, and shutdown conditions, and can also include the maximum value, typical value, and minimum value.

Logic synthesis

Concept

Verilog code written by designers is usually at a higher level of abstraction, such as the register transfer level. This level of abstraction contains a description of the transfer of circuit signals between registers. However, the netlist at the logic gate level, that is, the interconnection form of the logic gates, is the closest to the real hardware circuit. This form is functionally equivalent to the description of the register transfer level. In order to provide this kind of low abstraction level description to the subsequent hardware manufacturers, the Verilog code at high abstraction level needs to be converted into a logic gate level netlist at low abstraction level. This process is called Logic Synthesis.

Before the emergence of automated logic synthesis tools, although people can use hardware description languages for design, they still need to manually perform logic synthesis. For example, if the circuit module has only a few inputs, we can use a Karnaugh map-like method to simplify the logic function. As the scale of the circuit continues to increase, the shortcomings of error-prone and time-consuming synthesis of artificial logic are gradually highlighted. At the same time, the optimized synthesis results under a particular device process may not be suitable under another process. If another process is required, the designer needs to spend a long time to re-integrate the logic. With the emergence of automated logic synthesis tools, the hardware description language and the required device process information (process library) can be directly read by the logic synthesis tool. Through its internal automatic synthesis algorithm, the output meets the design constraints (usually including timing and power consumption) , Area constraints) logic gate-level netlist. With the help of automatic synthesis tools, designers can focus more on hardware description language design at a high level of abstraction.

Synthesizable code

Logic synthesis tools cannot accept all Verilog code. The designer needs to ensure that the hardware description language code is a cycle-to-cycle register transfer level description. Loop structures such as while must provide termination conditions in the form of signal edges (such as @(posedge clock)); initial structures may also not be converted. If you do not specify the bit width of the number, the system may default it to a larger value (such as 32 bits), which may result in a very large logic gate-level netlist, some of which are unnecessary, which will cause resources Waste. Operators related to unknown logic x and high-impedance state z cannot be converted, for example ===, !== In addition, if the conditional structure has only if without designing for the case of else, or the selection structure lacks the default, default, it is very Unexpected latches may be generated. Due to the need to use logic gates related to the process, user-defined primitives may not be converted. Designers need to adopt a good code style to obtain more optimized logic synthesis results. In order to adapt to the system chip and IP core design that conforms to reusable design ideas, designers should also follow stricter coding standards.

Advanced Features

Custom primitives

In addition to the 26 logic gate and transistor primitives provided by the system, Verilog also provides user-defined primitives (User Defined Primitive, UDP). The hierarchical structure of primitives and modules is similar, but the input and output relationship of primitives is completely achieved through table lookup. The core of the user-defined primitive of combinational logic is the truth table, and the core of the user-defined primitive of sequential logic is the incentive table. The designer needs to list possible input and output conditions in the status table. If, in actual use, encounter a situation that is not defined in the status table, an uncertain value x is output. Using custom primitives is intuitive, but if there are many input variables, the state table becomes very complicated. In many cases, user-defined primitives cannot be converted by logic synthesis tools.

Programming language interface

The Programming Language Interface (Program Language Interface, PLI) provides a way to store and read Verilog data structures through C language functions.

The development of the Verilog programming language interface has gone through three generations, of which the first generation is a task or function subroutine, which can transfer data between the C program and the Verilog design; the second generation is the access subroutine, which can be customized in the user C The program and Verilog's internal data representation interface are used; the third generation is the Verilog process interface, which further expands the functionality of the first two generations of programming language interfaces.

By using a programming language interface, designers can customize the functions of the interface, and then call these custom functions in a manner similar to calling system tasks. In this way, designers can greatly expand the functions they can use, such as monitoring, excitation, debugging functions, or use it to extract design information, display output, etc.

Related tools

As one of the most widely used hardware description languages in the industry, Verilog is supported by a large number of electronic design automation tools. By using an integrated development environment, designers can design, simulate, and verify in common Windows or other graphical systems, such as integrated circuit computer-aided design systems provided by companies such as Cadence and Synopsys.

Compared with VHDL

VHDL-VHSIC (Very High Speed Integrated Circuit) HDL, HDL supported by the US DOD, became the IEEE 1076-1987 standard in 1987, and was later revised to the IEEE 1076-1993 standard.

Verilog comes from C language, easy to learn and use, flexible and concise programming style, many users, especially popular in ASIC field;

VHDL comes from ADA, rigorous grammar, more difficult to learn, and more users in Europe and China;

The design levels described by the two are different:

„VHDL: system level, behavior level, RTL level, gate level

„VerilogHDL: behavior level, RTL level, gate level, switch level, not supported: circuit level (spice), layout level (GDSII/CIF)

Use

Verilog HDL is a hardware description language developed on the basis of the most widely used C language. It was first created by PhilMoorby of GDA (Gateway Design Automation) company at the end of 1983. Initially, only a simulation and verification tool was designed. Since then, related fault simulation and timing analysis tools have been developed. In 1985, Moorby launched its third commercial emulator Verilog-XL, which was a huge success, which enabled Verilog HDL to be quickly promoted and applied. In 1989, CADENCE acquired GDA, making VerilogHDL an exclusive patent for the company. In 1990, CADENCE publicly published Verilog HDL, and established the LVI organization to promote Verilog HDL to become the IEEE standard, ie IEEE Standard 1364-1995.

The biggest feature of Verilog HDL is that it is easy to learn and use. If you have programming experience in C language, you can learn and master it quickly in a short period of time. Therefore, you can arrange Verilog HDL content to be taught in related courses such as ASIC design. Because the HDL language itself is designed specifically for hardware and systems, this arrangement allows learners to gain experience in designing actual circuits at the same time. In contrast, VHDL is more difficult to learn. But Verilog HDL's freer grammar is also prone to make some mistakes for beginners, this should be noted.