Configure the end signal.
This is a dedicated configuration status pin. The bidirectional pin, when it is an output pin, is open drain. When used as a status output pin, it is set low before and during configuration. Once the configuration data is received and there are no errors, CONF_DONE will be released as soon as the initialization cycle begins. When used as a status input pin, after all data is received, it must be set to a high level. The device will then initialize and enter user mode. It cannot be used as normal I/O. This pin must be connected with a 10K ohm resistor.
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 240-Pin HSPQFP EP
This lends power savings to High-end Communication equipment and speed to battery operated devices.
This lends power savings to High-end Communication equipment and speed to battery operated devices.
FPGA Virtex-II Family 1.5M Gates 17280 Cells 650MHz 0.15um Technology 1.5V 575-Pin BGA
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