Configure status signals.
This is a dedicated configuration status pin. The bidirectional pin, when it is an output pin, is open drain. Immediately after power-on, the FPGA sets the nSTATUS pin to a low level, and after power-on reset (POR) is completed, release it and set it to a high level. As a status output pin, if any error occurs during configuration, the nSTATUS pin will be set low. When used as a status input pin, the external control chip can pull this pin low during configuration or initialization, and the FPGA will enter an error state. This pin cannot be used as a normal I/O pin. The nSTATUS pin must pull up a 10K ohm resistor.
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
Xilinx BGA
This lends power savings to High-end Communication equipment and speed to battery operated devices.
This lends power savings to High-end Communication equipment and speed to battery operated devices.
CPLD CoolRunner -II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um Technology 1.8V 56-Pin CSBGA
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