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FPGA configuration mode

FPGA has a variety of configuration modes: the parallel master mode is an FPGA plus an EPROM; the master-slave mode can support one PROM to program multiple FPGAs; the serial mode can use serial PROM to program the FPGA; the peripheral mode can use the FPGA as a micro The peripherals of the processor are programmed by the microprocessor.

　　 How to achieve fast timing closure, reduce power consumption and cost, optimize clock management, and reduce the complexity of FPGA and PCB parallel design, has always been a key issue for system design engineers who adopt FPGAs. Nowadays, as FPGAs develop towards higher density, larger capacity, lower power consumption and more IP integration, system design engineers have to face the unprecedented performance and performance of FPGAs while benefiting from these excellent performance. New design challenges brought about by ability level.

In many project designs, use Altera's Cyclone series devices based on SRAM architecture. Cyclone devices, like other FPGA devices, provide users with programmable resources based on gate arrays, and the formation of its internal logic structure is determined by configuration data. These configuration data can be loaded into the SRAM inside the FPGA through a variety of modes. Due to the volatile nature of SRAM, the FPGA must be reconfigured every time it is powered on.

　　1 Cyclone FPGA configuration mode

There are three main configuration schemes for Cyclone series FPGA devices, including active serial (AS) configuration using low-cost configuration chips, passive serial (PS) configuration, and JTAG-based configuration. In practical applications, you can use one of these solutions to configure the Cyclone series FPGA devices, to realize the functions that users need to program.

　　 Cyclone series FPGA devices use SRAM cells to configure data. Since SRAM is easy to lose data after power failure, configuration data must be downloaded to the powered Cyclone device immediately. Different configuration modes can use different dedicated configuration chips or data sources

These three configuration modes are determined by the high and low levels of the mode selection pins MSEL1 and MSEL0 of the Cyclone device. If your actual application requires only a single configuration mode, you can connect the mode selection pin to the VCC terminal or the ground terminal. In the process of switching pins, the operating state of the device will not be affected. In any case, before reconfiguration, the level of the mode selection pin must be guaranteed to be valid.

　　2 Configure the active serial (AS) configuration of the chip

In the AS configuration mode, new low-cost devices (such as EPCS1, EPCS4) are used. This dedicated configuration chip is a serial configuration device with a permanent memory and a simple four-pin interface. Because of its low cost, It can solve the problem of high cost of configuration devices. The serial configuration chip provides a serial interface to access data. During configuration, Cyclone FPGA reads the data through the serial interface, if necessary, decompresses the data and configures the SRAM cell of the FPGA. This mode is controlled by the FPGA to configure the interface. This scheme is called active serial configuration, or AS configuration for short. Schematic diagram of configuring a Cyclone FPGA device in AS mode

　　The dedicated serial configuration chip can choose EPCS1 or EPCS4. The storage space of EPCS1 is 1Mbits and the storage space of EPCS4 is 4Mbits. The designer can choose according to the size of the configuration file. The main configuration pins of the active serial configuration chip

DCLK, serial clock input terminal, from Cyclone FPGA device, provides serial interface clock; DATA, serial data output terminal, reads data on the falling edge of DCLK; ASDI, control signal input terminal, latches data on the rising edge of DCLK; nCS, enable input terminal, active low.

　　 During the system power-on period, the two chips enter the power-on reset phase. Once the power-on reset is entered, the nSTATUS terminal is low and resetting; at the same time, the CONF_DONE terminal is low and the chip has not been configured yet. After resetting, delay 100ms, FPGA releases nSTATUS end, because of the function of the pull-up resistor, this end becomes high level, enter the configuration state at this moment. Once exiting the reset, all user I/O terminals enter the tri-state state. The clock signal DCLK is generated inside the FPGA to control the entire configuration cycle and provide a clock for the configuration chip serial circuit. The frequency range of the clock signal is between 14MHZ and 20MHZ. When the falling edge of DCLK comes, the FPGA is made to output control signals and the configuration chip is made to output configuration data; when the rising edge of DCLK comes, the FPGA is made to latch the configuration data and the configuration chip is made to latch the control signal. After all the configuration data is received, FPGA releases the CONF_DONE end, sets it to a high level through a 10K pull-up resistor, and begins to enter the initialization phase. Cyclone FPGA devices require 136 clock cycles to strictly initialize. Then begin to enter the user state, at this time the INIT_DONE pin jumps to a high level.

3 Passive serial (PS) configuration based on microcontroller

　　 Simplified circuit diagram of Cyclone FPGA passive serial configuration scheme using microprocessor. The configuration process of the single-chip microcomputer is very simple. The single-chip microcomputer only needs 5 I/O ports to connect to the FPGA. The 5 signal lines are: DATA0, DCLK, nCONFIG, nSTATUS and CONF_DONE.

　　The specific configuration process is as follows: ①nCONFIG=0, DCLK=0, keep 2us or more; ②Check nSTATUS, if it is 0, it means that FPGA has responded to the configuration request and can start configuration, otherwise an error will be reported. Under normal conditions, nSTATUS will be 0 within 1us after nCONFIG=0; ③nCONFIG=0, and wait for 5us; ④Place data on DATA0, DCLK=1, delay; ⑤DCLK=0, check nSTATUS, if it is 0, report an error and restart Start; ⑥Prepare the next bit of data, and repeat (4), (5) until all the data is sent; ⑦At this time, CONF_DONE should become 1, indicating that the FPGA configuration has been completed. If all the data is sent out, CONF_DONE is not 1, it must be reconfigured; ⑧After the configuration is completed, send out several cycles of DCLK to make the FPGA complete initialization.

　　 It is worth noting that the SOF or POF file generated with MAX+PlusⅡ or QuartusⅡ cannot be directly used for the MCU to configure the FPGA. Data conversion is required to obtain the usable configuration data. In MAX+PlusⅡ or QuartusⅡ, there is a data conversion option. The .SOF file is converted to a .rbf file, and then the .rbf file is directly written into a certain ROM or Flash area of the microcontroller system. The starting address of this piece of data Both the length and the length are known, just write the corresponding software according to the above process.

　　4 Configure data compression method

Cyclone device is an FPGA device that supports decompression of configuration data, allowing configuration data stored in the configuration chip or other memory to be compressed data. During configuration, this compressed data is sent to the Cyclone device to be immediately decompressed and SRAM The unit is programmed. Both the AS configuration mode and the PS configuration mode support compression, but the JTAG-based configuration mode does not support compression. Preliminary data shows that compression can reduce the configuration data bit stream by 35% to 60%, which can reduce the storage space and transmission speed of data and the cost of configuration equipment.

　　QuartusⅡ can generate compressed configuration files, which can reduce the transmission time of configuration chip and flash memory space and bit stream. The following takes Quartus II version 5.1 as an example to introduce two methods of compressing configuration files.

　　4.1 Method 1: Activate compression in the project program settings before designing the program.

　　 First click on the Device item under the Assignments menu to pop up the SetTIngs window, then select the Cyclone device in the Family option, click the Device&Pin OpTIons pop-up window below, and then select the ConfiguraTIon window and click Generate Compressed bitstreams option, and finally press the OK button to end the setting.

　　4.2 Method 2: After the design program is written, create a program file from the Convert Programming Files window to activate compression.

First pull down the File menu, click the Convert Programming Files pop-up window, select the file type Programming File type (POF, SRAM HEXOUT, RBF, orTTF), then for POF output files, select the configuration device, and then select Add File to add a Cyclone SOF file, select The file name is added to the SOF Data area, click the ProperTIes option, then confirm, and finally press the Generate button to generate.