The device in the download chain can be input, connected to the nCEO of the previous device, and the last device in the download chain, nCE, is grounded.
Dedicated input pin. This pin is an active low chip select enable signal. The nCE pin is the configuration enable pin. In configuration, initialization and user mode, the nCE pin must be set low. In the configuration process of multiple devices, the nCE pin of the first device should be set low, and its nCEO should be connected to the nCE pin of the next device, forming a chain. The nCE pin also needs to be set low when using the JTAG programming mode. This pin has an input buffer to support the hysteresis function of Schmitt trigger.
FPGA XC4000A Family 2K Gates 64 Cells 125MHz 5V 84-Pin PLCC
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 304-Pin HSPQFP EP
This lends power savings to High-end Communication equipment and speed to battery operated devices.
Xilinx QFP100
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