(I/O) FPGA serial data output, connected to the ASDI pin of the configuration device.
It is a dedicated output pin in AS mode and can be used as an I/O pin in PS and JTAG modes. In AS mode, this pin is the pin that CII sends control signals to the serial configuration chip. It is also used to read configuration data from the configuration chip. In AS mode, ASDO has an internal pull-up resistor, which is always effective. After the configuration is completed, this pin becomes a tri-state input pin. The ASDO pin is directly connected to the ASDI pin (Pin 5) of the configuration chip.
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 770MHz 90nm Technology 1.2V 676-Pin FBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
Xilinx BGA
This lends power savings to High-end Communication equipment and speed to battery operated devices.
This lends power savings to High-end Communication equipment and speed to battery operated devices.
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