(I/O) FPGA chip select signal output, connected to the nCS pin of the configuration device.
It is a dedicated output pin in AS mode and can be used as an I/O pin in PS and JTAG modes. In AS mode, this pin is an enable pin used by CII to send to the external serial configuration chip. In AS mode, ASDO has an internal pull-up resistor, which is always active. This pin is active low. Connect directly to the /CS pin (pin 1) of the configuration chip.
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CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
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FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 256-Pin BGA
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