It is input in PS mode and output in AS mode. In PS mode, DCLK is a clock input pin, which is the clock used by external devices to transfer configuration data to the FPGA. Data is the data on the rising edge of DCLK. In AS mode, the DCLK pin is a clock output pin, which is to provide a configuration clock. Connect directly to the DCLK pin of the configuration chip (pin 6). Regardless of the configuration mode, this pin will become tri-stated after configuration is complete. If the external device is a configuration device, the configuration device will set the DCLK pin to low level. If you are using a master chip, you can either set DCLK high or DCLK low. After the configuration is complete, triggering this pin will not affect the configured FPGA. This pin has an input buffer to support the hysteresis function of Schmitt trigger.
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 770MHz 90nm Technology 1.2V 484-Pin LCSBGA
FPGA XC4000A Family 2K Gates 64 Cells 125MHz 5V 84-Pin PLCC
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 304-Pin HSPQFP EP
This lends power savings to High-end Communication equipment and speed to battery operated devices.