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Home > Wiki encyclopedia > DCLK


It is input in PS mode and output in AS mode. In PS mode, DCLK is a clock input pin, which is the clock used by external devices to transfer configuration data to the FPGA. Data is the data on the rising edge of DCLK. In AS mode, the DCLK pin is a clock output pin, which is to provide a configuration clock. Connect directly to the DCLK pin of the configuration chip (pin 6). Regardless of the configuration mode, this pin will become tri-stated after configuration is complete. If the external device is a configuration device, the configuration device will set the DCLK pin to low level. If you are using a master chip, you can either set DCLK high or DCLK low. After the configuration is complete, triggering this pin will not affect the configured FPGA. This pin has an input buffer to support the hysteresis function of Schmitt trigger.


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