Dedicated input pin. In AS mode, the configuration process is: CII sets nCSO low and the configuration chip is enabled. CII then cooperates with DDO and ASDO to send operation commands and read addresses to the configuration chip. Configure the chip and then send data to CII through the DATA pin. The DATA pin is connected to the DATA0 pin of CII. After CII receives all the configuration data, it will release the CONF_DONE pin (that is, it is not forced to make the CONF_DONE pin low), and the CONF_DONE pin is open-drain. At this time, because CONF_DONE will be connected to a 10K resistor externally, it will become a high level. At the same time, CII stops the DCLK signal. After CONF_DONE becomes high level (it is equivalent to becoming an input pin at this time), the initialization process begins. Therefore, a 10K resistor must be connected outside the CONF_DONE pin to ensure that the initialization process can start correctly. DATA0, DCLK, NCSO, ASDO have weak pull-up resistors and are always valid. After the configuration is completed, these pins will become input three-state, and the level will be set to high level by a weak internal pull-up resistor. In AS mode, DATA0 is connected to the DATA (pin 2) of the configuration chip.
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CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 240-Pin HSPQFP EP
This lends power savings to High-end Communication equipment and speed to battery operated devices.
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