The circuit structure mask implemented on an ASIC device is verified to be correct and the total number of gates is more than 5000 gates.
The hard core (hard core), specially designed for the IP core used in the layout stage, is submitted in the form of a layout. The hard core is a core that has been optimized for performance, power consumption, and geometry, and is mapped to a specified process and verified by actual tape-out. When in use, as long as it conforms to the overall IC process, the core that meets the physical limitations of this core can be used. It is the simplest to use, but it loses flexibility.
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 676-Pin FBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 770MHz 90nm Technology 1.2V 484-Pin LCSBGA
FPGA XC4000A Family 2K Gates 64 Cells 125MHz 5V 84-Pin PLCC
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
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