The solid core (firm core), because the design stage used is between the soft core and the hard core, so its IP core is called the solid core. It is submitted in the form of integrated code or a general library netlist. Because of the structural or topological optimization of the performance and geometry, etc., and the preliminary mapping of multiple processes, the flexibility of the user is between the hard and soft cores.
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 324-Pin FBGA
FPGA Spartan-XL Family 20K Gates 950 Cells 217MHz 3.3V 208-Pin HSPQFP EP
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 676-Pin FBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 770MHz 90nm Technology 1.2V 676-Pin FBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA