SGMII (Serial Gigabit Media Independent Interface), since it is serial, the data bit width is 1 bit, and there is a pair of differential signal lines for transmission and reception. The working clock is provided by the PHY and the frequency is 625M. Both the rising and falling edges of the clock are sampled. The IP core performs 8b/10b encoding on the serial data, so the effective data transmission rate is 625M*1bit*2*8b/10b=1000Mbps.
Regarding this 8/10b encoding, it was first invented and applied by IBM, and it is reflected in pcie, hdmi and USB interfaces. 8/10b encoding is a commonly used encoding method for high-speed serial buses. In order to ensure DC balance (0 in the data stream) The number of /1 is basically the same, no more than 5 consecutive 0/1). . . The first 8 bits of the 8/10b code that minimizes the transmission of differential signals in HDMI are obtained from the original data after the operation. The 9th bit is the "operation mode bit", indicating whether the first 8 bits are encoded in an XOR or XOR mode. The 10-bit is to ensure DC balance.
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 256-Pin FTBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 208-Pin PQFP
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 676-Pin FBGA
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