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RGMII

RGMII (Reduced Gigabit Media Independent Interface) is Reduced GMII (Gigabit Media Independent Interface). RGMII adopts 4-bit data interface, working clock 125MHz, and transmits data at the rising and falling edges at the same time, so the transmission rate can reach 1000Mbps.

Introduction

At the same time, it is compatible with the 10/100 Mbps working mode specified by MII, and supports the transmission rate: 10M/100M/1000Mb/s, and the corresponding clk signals are: 2.5MHz/25MHz/125MHz. The RGMII data structure conforms to the IEEE Ethernet standard. For the interface definition, see IEEE 802.3-2000.

The purpose of using RGMII is to reduce the cost of the circuit and reduce the number of pins of the device implementing this interface from 25 to 14.

Communication principle

Generally used for communication between MAC and PHY.

Transmitter:

◎ GTX_CLK——Gigabit TX.. signal clock signal (125MHz)

◎ TXD[3..0]——Sent data

◎ TX_CTL——Transmission control

Note: At the Gigabit rate, the GTX_CLK signal is provided to the PHY, and the TXD, TXEN, and TXER signals are synchronized with this clock signal. Otherwise, at the 10/100M rate, the PHY provides the TXCLK clock signal, and other signals are synchronized with this signal. Its operating frequency is 25MHz (100M network) or 2.5MHz (10M network).

receiver:

◎ RX_CLK——Receive clock signal (extracted from the received data, so it is not related to GTXCLK)

◎ RXD[3..0]——Receive data

◎ RX_CTL——Reception control

◎ COL——Collision detection (only for half-duplex state)

◎ CRS——Carrier monitoring

Management configuration (control and status information):

◎ MDC——Configure interface clock

◎ MDIO——Configure interface I/O

Compared with the GMII interface, the RGMII interface reduces a total of 8 data lines on TXD and RXD.

RGMII is a reduced pin count interface that can simplify design by reducing the interface pin count from the 25pins used in the GMII interface to 12. It can lower system cost compared to existing GMII or TBI interfaces by reducing the number of layers required to route high density networking solutions. Using RGMII, fewer pins are required for the MAC/switch ASIC, which can reduce the MAC/switch cost by enabling smaller die sizes than would be possible with GMII or TBI. However, the RGMII specification calls for a timing delay on both the receive signal and the transmit signal for each port that must be implemented in a board level trace. These trace lengths are typically arranged in a spiral on the board that takes approximately one square inch of board space per trace. Broadcom offers an alternative timing solution that eliminates the need for the timing delay traces. Assuming a one-inch space requirement per trace for both transmit and receive signals on 48 ports, elimination of the timing delay traces can save 96 square inches of layout space.

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