This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > Flip-Flop


Trigger Flip-Flop: The input pulse is received, and the trigger output is changed according to the assignment rule. Keep this state until the next trigger. . . Sensitive to the clock edge, its state changes only at the instant of the rising or falling edge of the clock;

Difference latch

The latch is related to all its input signals. When the input signal changes, the latch changes without clock triggering; flip_flop is controlled by the clock, and the current input is sampled only when the clock edge is triggered to generate output.

1) Latch is triggered by level and controlled asynchronously. When the enable signal is valid, the latch is equivalent to the channel, and when the enable signal is invalid, the latch maintains the output state; flip_flop is triggered by the clock edge, and is synchronously controlled;

2) The latch is sensitive to the input level and is greatly affected by the wiring delay. It is difficult to ensure that the output does not generate glitches; flip_flop is not easy to generate glitches;

3) Latch consumes less gate resources than flip_flop, but its static timing analysis is more complicated.


It is a circuit that produces an output value of 0 or 1 that remains constant until a temporary pulse (a temporary change to a 1 that returns to 0) from another circuit causes it to shift to the other value. In other word, the output will flip or flop between two values under control of external stimuli.


  • XC3SD3400A-4CS484I


    FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA

  • XC5VFX100T-1FF1136I


    FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA

  • XC2C512-10FT256I


    CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 256-Pin FTBGA

  • XC2C512-10PQG208I


    CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 208-Pin PQFP

  • XC2C512-7FT256I


    CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA

FPGA Tutorial Lattice FPGA
Need Help?


If you have any questions about the product and related issues, Please contact us.