Latch: two inputs, EN and DATA_IN, when the level EN is valid, the latch is in the enabled state, the output data Q changes with the input data DATA_IN, otherwise the data is latched.
Xilinx BGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 256-Pin FTBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 324-Pin FBGA
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