The edge scan test was developed in the mid-1980s as a JTAG interface to solve the PCB physical access problem. Such a problem is caused by the increasingly crowded circuit board assembly caused by the new packaging technology.
Boundary scan embeds test circuits at the chip level to form a comprehensive board-level test protocol. With boundary scan—the industry standard IEEE 1149.1 since 1990—you can even test, debug, and program in-system devices on even the most complex assemblies, and diagnose hardware problems.
Boundary scan priority:
By providing IO access to the scan chain, the need for physical test points on the circuit board can be eliminated or greatly reduced, which will result in significant cost savings because the circuit board layout is simpler, the test fixture is cheaper, and the test system in the circuit Less time-consuming, increased use of standard interfaces, and faster time to market. In addition to circuit board testing, boundary scan allows programming of almost all types of CPLDs and flash memories on the circuit board after PCB placement, regardless of size or package type. In-system programming can save costs and increase production by reducing equipment handling, simplifying inventory management, and integrating programming steps on the circuit board production line.
The IEEE 1149.1 standard specifies a four-wire serial interface (the fifth wire is optional). This interface is called the test access port (TAP) and is used to access complex integrated circuits (ICs), such as microprocessors, DSPs. , ASIC and CPLD. In addition to TAP, hybrid ICs also contain shift registers and state machines to perform boundary scan functions. The data input into the chip on the TDI (Test Data Input) lead is stored in the instruction register or a data register. Serial data leaves the chip from the TDO (Test Data Output) lead. The boundary scan logic is clocked by the signal on the TCK (test clock), and the TMS (test mode selection) signal drives the state of the TAP controller. TRST (Test Reset) is optional. Multiple ICs compatible with scanning functions can be serially interconnected on the PCB to form one or more scanning chains, each of which has its own TAP. Each scan chain provides electrical access, from the serial TAP interface to each lead on each IC that is part of the chain. During normal operation, the IC performs its intended function as if the boundary scan circuit did not exist. However, when the device's scan logic is activated for testing or system programming, data can be transferred to the IC and read from the IC using a serial interface. This data can be used to activate the device core, send signals from the device leads to the PCB, read the PCB input leads and read the device output.
FPGA Spartan-3A DSP Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin CSBGA
FPGA Spartan-3A DSP Family 1.8M Gates 37440 Cells 770MHz 90nm Technology 1.2V 676-Pin FBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 256-Pin FTBGA